2 * TI DaVinci Power and Sleep Controller (PSC)
4 * Copyright (C) 2006 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/kernel.h>
22 #include <linux/init.h>
25 #include <mach/cputype.h>
28 /* PSC register offsets */
37 #define MDSTAT_STATE_MASK 0x1f
39 /* Return nonzero iff the domain's clock is active */
40 int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
42 void __iomem *psc_base;
44 struct davinci_soc_info *soc_info = &davinci_soc_info;
46 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
47 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
48 (int)soc_info->psc_bases, ctlr);
52 psc_base = soc_info->psc_bases[ctlr];
53 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
55 /* if clocked, state can be "Enable" or "SyncReset" */
56 return mdstat & BIT(12);
59 /* Enable or disable a PSC domain */
60 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
61 unsigned int id, char enable)
63 u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
64 void __iomem *psc_base;
65 struct davinci_soc_info *soc_info = &davinci_soc_info;
66 u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
68 if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
69 pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
70 (int)soc_info->psc_bases, ctlr);
74 psc_base = soc_info->psc_bases[ctlr];
76 mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
77 mdctl &= ~MDSTAT_STATE_MASK;
79 __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
81 pdstat = __raw_readl(psc_base + PDSTAT);
82 if ((pdstat & 0x00000001) == 0) {
83 pdctl1 = __raw_readl(psc_base + PDCTL1);
85 __raw_writel(pdctl1, psc_base + PDCTL1);
88 __raw_writel(ptcmd, psc_base + PTCMD);
91 epcpr = __raw_readl(psc_base + EPCPR);
92 } while ((((epcpr >> domain) & 1) == 0));
94 pdctl1 = __raw_readl(psc_base + PDCTL1);
96 __raw_writel(pdctl1, psc_base + PDCTL1);
99 ptstat = __raw_readl(psc_base +
101 } while (!(((ptstat >> domain) & 1) == 0));
104 __raw_writel(ptcmd, psc_base + PTCMD);
107 ptstat = __raw_readl(psc_base + PTSTAT);
108 } while (!(((ptstat >> domain) & 1) == 0));
112 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
113 } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));