2 * DaVinci timer subsystem
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/clocksource.h>
16 #include <linux/clockchips.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
22 #include <mach/hardware.h>
23 #include <asm/mach/irq.h>
24 #include <asm/mach/time.h>
25 #include <mach/cputype.h>
26 #include <mach/time.h>
29 static struct clock_event_device clockevent_davinci;
30 static unsigned int davinci_clock_tick_rate;
33 * This driver configures the 2 64-bit count-up timers as 4 independent
34 * 32-bit count-up timers used as follows:
42 /* Timer register offsets */
52 /* Offsets of the 8 compare registers */
62 /* Timer register bitfields */
63 #define TCR_ENAMODE_DISABLE 0x0
64 #define TCR_ENAMODE_ONESHOT 0x1
65 #define TCR_ENAMODE_PERIODIC 0x2
66 #define TCR_ENAMODE_MASK 0x3
68 #define TGCR_TIMMODE_SHIFT 2
69 #define TGCR_TIMMODE_64BIT_GP 0x0
70 #define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
71 #define TGCR_TIMMODE_64BIT_WDOG 0x2
72 #define TGCR_TIMMODE_32BIT_CHAINED 0x3
74 #define TGCR_TIM12RS_SHIFT 0
75 #define TGCR_TIM34RS_SHIFT 1
76 #define TGCR_RESET 0x0
77 #define TGCR_UNRESET 0x1
78 #define TGCR_RESET_MASK 0x3
80 #define WDTCR_WDEN_SHIFT 14
81 #define WDTCR_WDEN_DISABLE 0x0
82 #define WDTCR_WDEN_ENABLE 0x1
83 #define WDTCR_WDKEY_SHIFT 16
84 #define WDTCR_WDKEY_SEQ0 0xa5c6
85 #define WDTCR_WDKEY_SEQ1 0xda7e
94 unsigned long tim_off;
95 unsigned long prd_off;
96 unsigned long enamode_shift;
97 struct irqaction irqaction;
99 static struct timer_s timers[];
101 /* values for 'opts' field of struct timer_s */
102 #define TIMER_OPTS_DISABLED 0x01
103 #define TIMER_OPTS_ONESHOT 0x02
104 #define TIMER_OPTS_PERIODIC 0x04
105 #define TIMER_OPTS_STATE_MASK 0x07
107 #define TIMER_OPTS_USE_COMPARE 0x80000000
108 #define USING_COMPARE(t) ((t)->opts & TIMER_OPTS_USE_COMPARE)
110 static char *id_to_name[] = {
111 [T0_BOT] = "timer0_0",
112 [T0_TOP] = "timer0_1",
113 [T1_BOT] = "timer1_0",
114 [T1_TOP] = "timer1_1",
117 static int timer32_config(struct timer_s *t)
120 struct davinci_soc_info *soc_info = &davinci_soc_info;
122 if (USING_COMPARE(t)) {
123 struct davinci_timer_instance *dtip =
124 soc_info->timer_info->timers;
125 int event_timer = ID_TO_TIMER(timers[TID_CLOCKEVENT].id);
128 * Next interrupt should be the current time reg value plus
129 * the new period (using 32-bit unsigned addition/wrapping
130 * to 0 on overflow). This assumes that the clocksource
131 * is setup to count to 2^32-1 before wrapping around to 0.
133 __raw_writel(__raw_readl(t->base + t->tim_off) + t->period,
134 t->base + dtip[event_timer].cmp_off);
136 tcr = __raw_readl(t->base + TCR);
139 tcr &= ~(TCR_ENAMODE_MASK << t->enamode_shift);
140 __raw_writel(tcr, t->base + TCR);
142 /* reset counter to zero, set new period */
143 __raw_writel(0, t->base + t->tim_off);
144 __raw_writel(t->period, t->base + t->prd_off);
146 /* Set enable mode */
147 if (t->opts & TIMER_OPTS_ONESHOT)
148 tcr |= TCR_ENAMODE_ONESHOT << t->enamode_shift;
149 else if (t->opts & TIMER_OPTS_PERIODIC)
150 tcr |= TCR_ENAMODE_PERIODIC << t->enamode_shift;
152 __raw_writel(tcr, t->base + TCR);
157 static inline u32 timer32_read(struct timer_s *t)
159 return __raw_readl(t->base + t->tim_off);
162 static irqreturn_t timer_interrupt(int irq, void *dev_id)
164 struct clock_event_device *evt = &clockevent_davinci;
166 evt->event_handler(evt);
170 /* called when 32-bit counter wraps */
171 static irqreturn_t freerun_interrupt(int irq, void *dev_id)
176 static struct timer_s timers[] = {
178 .name = "clockevent",
179 .opts = TIMER_OPTS_DISABLED,
181 .flags = IRQF_DISABLED | IRQF_TIMER,
182 .handler = timer_interrupt,
185 [TID_CLOCKSOURCE] = {
186 .name = "free-run counter",
188 .opts = TIMER_OPTS_PERIODIC,
190 .flags = IRQF_DISABLED | IRQF_TIMER,
191 .handler = freerun_interrupt,
196 static void __init timer_init(void)
198 struct davinci_soc_info *soc_info = &davinci_soc_info;
199 struct davinci_timer_instance *dtip = soc_info->timer_info->timers;
200 void __iomem *base[2];
203 /* Global init of each 64-bit timer as a whole */
207 base[i] = ioremap(dtip[i].base, SZ_4K);
208 if (WARN_ON(!base[i]))
211 /* Disabled, Internal clock source */
212 __raw_writel(0, base[i] + TCR);
214 /* reset both timers, no pre-scaler for timer34 */
216 __raw_writel(tgcr, base[i] + TGCR);
218 /* Set both timers to unchained 32-bit */
219 tgcr = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
220 __raw_writel(tgcr, base[i] + TGCR);
223 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
224 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
225 __raw_writel(tgcr, base[i] + TGCR);
227 /* Init both counters to zero */
228 __raw_writel(0, base[i] + TIM12);
229 __raw_writel(0, base[i] + TIM34);
232 /* Init of each timer as a 32-bit timer */
233 for (i=0; i< ARRAY_SIZE(timers); i++) {
234 struct timer_s *t = &timers[i];
235 int timer = ID_TO_TIMER(t->id);
238 t->base = base[timer];
242 if (IS_TIMER_BOT(t->id)) {
243 t->enamode_shift = 6;
246 irq = dtip[timer].bottom_irq;
248 t->enamode_shift = 22;
251 irq = dtip[timer].top_irq;
254 /* Register interrupt */
255 t->irqaction.name = t->name;
256 t->irqaction.dev_id = (void *)t;
258 if (t->irqaction.handler != NULL) {
259 irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
260 setup_irq(irq, &t->irqaction);
268 static cycle_t read_cycles(struct clocksource *cs)
270 struct timer_s *t = &timers[TID_CLOCKSOURCE];
272 return (cycles_t)timer32_read(t);
276 * Kernel assumes that sched_clock can be called early but may not have
279 static cycle_t read_dummy(struct clocksource *cs)
285 static struct clocksource clocksource_davinci = {
288 .mask = CLOCKSOURCE_MASK(32),
290 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
294 * Overwrite weak default sched_clock with something more precise
296 unsigned long long notrace sched_clock(void)
298 const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci);
300 return clocksource_cyc2ns(cyc, clocksource_davinci.mult,
301 clocksource_davinci.shift);
307 static int davinci_set_next_event(unsigned long cycles,
308 struct clock_event_device *evt)
310 struct timer_s *t = &timers[TID_CLOCKEVENT];
317 static void davinci_set_mode(enum clock_event_mode mode,
318 struct clock_event_device *evt)
320 struct timer_s *t = &timers[TID_CLOCKEVENT];
323 case CLOCK_EVT_MODE_PERIODIC:
324 t->period = davinci_clock_tick_rate / (HZ);
325 t->opts &= ~TIMER_OPTS_STATE_MASK;
326 t->opts |= TIMER_OPTS_PERIODIC;
329 case CLOCK_EVT_MODE_ONESHOT:
330 t->opts &= ~TIMER_OPTS_STATE_MASK;
331 t->opts |= TIMER_OPTS_ONESHOT;
333 case CLOCK_EVT_MODE_UNUSED:
334 case CLOCK_EVT_MODE_SHUTDOWN:
335 t->opts &= ~TIMER_OPTS_STATE_MASK;
336 t->opts |= TIMER_OPTS_DISABLED;
338 case CLOCK_EVT_MODE_RESUME:
343 static struct clock_event_device clockevent_davinci = {
344 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
346 .set_next_event = davinci_set_next_event,
347 .set_mode = davinci_set_mode,
351 static void __init davinci_timer_init(void)
353 struct clk *timer_clk;
354 struct davinci_soc_info *soc_info = &davinci_soc_info;
355 unsigned int clockevent_id;
356 unsigned int clocksource_id;
357 static char err[] __initdata = KERN_ERR
358 "%s: can't register clocksource!\n";
361 clockevent_id = soc_info->timer_info->clockevent_id;
362 clocksource_id = soc_info->timer_info->clocksource_id;
364 timers[TID_CLOCKEVENT].id = clockevent_id;
365 timers[TID_CLOCKSOURCE].id = clocksource_id;
368 * If using same timer for both clock events & clocksource,
369 * a compare register must be used to generate an event interrupt.
370 * This is equivalent to a oneshot timer only (not periodic).
372 if (clockevent_id == clocksource_id) {
373 struct davinci_timer_instance *dtip =
374 soc_info->timer_info->timers;
375 int event_timer = ID_TO_TIMER(clockevent_id);
377 /* Only bottom timers can use compare regs */
378 if (IS_TIMER_TOP(clockevent_id))
379 pr_warning("davinci_timer_init: Invalid use"
380 " of system timers. Results unpredictable.\n");
381 else if ((dtip[event_timer].cmp_off == 0)
382 || (dtip[event_timer].cmp_irq == 0))
383 pr_warning("davinci_timer_init: Invalid timer instance"
384 " setup. Results unpredictable.\n");
386 timers[TID_CLOCKEVENT].opts |= TIMER_OPTS_USE_COMPARE;
387 clockevent_davinci.features = CLOCK_EVT_FEAT_ONESHOT;
391 timer_clk = clk_get(NULL, "timer0");
392 BUG_ON(IS_ERR(timer_clk));
393 clk_enable(timer_clk);
398 davinci_clock_tick_rate = clk_get_rate(timer_clk);
400 /* setup clocksource */
401 clocksource_davinci.read = read_cycles;
402 clocksource_davinci.name = id_to_name[clocksource_id];
403 clocksource_davinci.mult =
404 clocksource_khz2mult(davinci_clock_tick_rate/1000,
405 clocksource_davinci.shift);
406 if (clocksource_register(&clocksource_davinci))
407 printk(err, clocksource_davinci.name);
409 /* setup clockevent */
410 clockevent_davinci.name = id_to_name[timers[TID_CLOCKEVENT].id];
411 clockevent_davinci.mult = div_sc(davinci_clock_tick_rate, NSEC_PER_SEC,
412 clockevent_davinci.shift);
413 clockevent_davinci.max_delta_ns =
414 clockevent_delta2ns(0xfffffffe, &clockevent_davinci);
415 clockevent_davinci.min_delta_ns = 50000; /* 50 usec */
417 clockevent_davinci.cpumask = cpumask_of(0);
418 clockevents_register_device(&clockevent_davinci);
420 for (i=0; i< ARRAY_SIZE(timers); i++)
421 timer32_config(&timers[i]);
424 struct sys_timer davinci_timer = {
425 .init = davinci_timer_init,
429 /* reset board using watchdog timer */
430 void davinci_watchdog_reset(struct platform_device *pdev)
436 base = ioremap(pdev->resource[0].start, SZ_4K);
440 wd_clk = clk_get(&pdev->dev, NULL);
441 if (WARN_ON(IS_ERR(wd_clk)))
445 /* disable, internal clock source */
446 __raw_writel(0, base + TCR);
448 /* reset timer, set mode to 64-bit watchdog, and unreset */
450 __raw_writel(tgcr, base + TGCR);
451 tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
452 tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
453 (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
454 __raw_writel(tgcr, base + TGCR);
456 /* clear counter and period regs */
457 __raw_writel(0, base + TIM12);
458 __raw_writel(0, base + TIM34);
459 __raw_writel(0, base + PRD12);
460 __raw_writel(0, base + PRD34);
462 /* put watchdog in pre-active state */
463 wdtcr = __raw_readl(base + WDTCR);
464 wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
465 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
466 __raw_writel(wdtcr, base + WDTCR);
468 /* put watchdog in active state */
469 wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
470 (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
471 __raw_writel(wdtcr, base + WDTCR);
473 /* write an invalid value to the WDKEY field to trigger
474 * a watchdog reset */
476 __raw_writel(wdtcr, base + WDTCR);