2 * arch/arm/mach-dove/irq.c
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/gpio.h>
16 #include <asm/mach/arch.h>
18 #include <asm/mach/irq.h>
20 #include <mach/bridge-regs.h>
21 #include <plat/orion-gpio.h>
24 static void pmu_irq_mask(struct irq_data *d)
26 int pin = irq_to_pmu(d->irq);
29 u = readl(PMU_INTERRUPT_MASK);
30 u &= ~(1 << (pin & 31));
31 writel(u, PMU_INTERRUPT_MASK);
34 static void pmu_irq_unmask(struct irq_data *d)
36 int pin = irq_to_pmu(d->irq);
39 u = readl(PMU_INTERRUPT_MASK);
41 writel(u, PMU_INTERRUPT_MASK);
44 static void pmu_irq_ack(struct irq_data *d)
46 int pin = irq_to_pmu(d->irq);
49 u = ~(1 << (pin & 31));
50 writel(u, PMU_INTERRUPT_CAUSE);
53 static struct irq_chip pmu_irq_chip = {
55 .irq_mask = pmu_irq_mask,
56 .irq_unmask = pmu_irq_unmask,
57 .irq_ack = pmu_irq_ack,
60 static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
62 unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
64 cause &= readl(PMU_INTERRUPT_MASK);
66 do_bad_IRQ(irq, desc);
70 for (irq = 0; irq < NR_PMU_IRQS; irq++) {
71 if (!(cause & (1 << irq)))
73 irq = pmu_to_irq(irq);
74 generic_handle_irq(irq);
78 static int __initdata gpio0_irqs[4] = {
85 static int __initdata gpio1_irqs[4] = {
92 static int __initdata gpio2_irqs[4] = {
99 void __init dove_init_irq(void)
103 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
104 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
107 * Initialize gpiolib for GPIOs 0-71.
109 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
110 IRQ_DOVE_GPIO_START, gpio0_irqs);
112 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
115 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
119 * Mask and clear PMU interrupts
121 writel(0, PMU_INTERRUPT_MASK);
122 writel(0, PMU_INTERRUPT_CAUSE);
124 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
125 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
126 irq_set_status_flags(i, IRQ_LEVEL);
127 set_irq_flags(i, IRQF_VALID);
129 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);