2 * arch/arm/mach-dove/irq.c
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/gpio.h>
16 #include <asm/mach/arch.h>
18 #include <asm/mach/irq.h>
20 #include <mach/bridge-regs.h>
23 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
26 BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
28 irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
29 3 + irq - IRQ_DOVE_GPIO_24_31;
31 orion_gpio_irq_handler(irqoff << 3);
32 if (irq == IRQ_DOVE_HIGH_GPIO) {
33 orion_gpio_irq_handler(40);
34 orion_gpio_irq_handler(48);
35 orion_gpio_irq_handler(56);
39 static void pmu_irq_mask(struct irq_data *d)
41 int pin = irq_to_pmu(d->irq);
44 u = readl(PMU_INTERRUPT_MASK);
45 u &= ~(1 << (pin & 31));
46 writel(u, PMU_INTERRUPT_MASK);
49 static void pmu_irq_unmask(struct irq_data *d)
51 int pin = irq_to_pmu(d->irq);
54 u = readl(PMU_INTERRUPT_MASK);
56 writel(u, PMU_INTERRUPT_MASK);
59 static void pmu_irq_ack(struct irq_data *d)
61 int pin = irq_to_pmu(d->irq);
64 u = ~(1 << (pin & 31));
65 writel(u, PMU_INTERRUPT_CAUSE);
68 static struct irq_chip pmu_irq_chip = {
70 .irq_mask = pmu_irq_mask,
71 .irq_unmask = pmu_irq_unmask,
72 .irq_ack = pmu_irq_ack,
75 static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
77 unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
79 cause &= readl(PMU_INTERRUPT_MASK);
81 do_bad_IRQ(irq, desc);
85 for (irq = 0; irq < NR_PMU_IRQS; irq++) {
86 if (!(cause & (1 << irq)))
88 irq = pmu_to_irq(irq);
89 generic_handle_irq(irq);
93 void __init dove_init_irq(void)
97 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
98 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
101 * Initialize gpiolib for GPIOs 0-71.
103 orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
104 IRQ_DOVE_GPIO_START);
105 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
106 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
107 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
108 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
110 orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
111 IRQ_DOVE_GPIO_START + 32);
112 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
114 orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
115 IRQ_DOVE_GPIO_START + 64);
118 * Mask and clear PMU interrupts
120 writel(0, PMU_INTERRUPT_MASK);
121 writel(0, PMU_INTERRUPT_CAUSE);
123 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
124 set_irq_chip(i, &pmu_irq_chip);
125 set_irq_handler(i, handle_level_irq);
126 irq_set_status_flags(i, IRQ_LEVEL);
127 set_irq_flags(i, IRQF_VALID);
129 set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);