2 * arch/arm/mach-dove/pcie.c
4 * PCIe functions for Marvell Dove 88AP510 SoC
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <video/vga.h>
14 #include <asm/mach/pci.h>
15 #include <asm/mach/arch.h>
16 #include <asm/setup.h>
17 #include <asm/delay.h>
18 #include <plat/pcie.h>
19 #include <mach/irqs.h>
20 #include <mach/bridge-regs.h>
21 #include <plat/addr-map.h>
29 char io_space_name[16];
30 char mem_space_name[16];
31 struct resource res[2];
34 static struct pcie_port pcie_port[2];
35 static int num_pcie_ports;
38 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
42 if (nr >= num_pcie_ports)
46 sys->private_data = pp;
47 pp->root_bus_nr = sys->busnr;
50 * Generic PCIe unit setup.
52 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
54 orion_pcie_setup(pp->base);
59 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
60 "PCIe %d I/O", pp->index);
61 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
62 pp->res[0].name = pp->io_space_name;
64 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
65 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
67 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
68 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
70 pp->res[0].flags = IORESOURCE_IO;
71 if (request_resource(&ioport_resource, &pp->res[0]))
72 panic("Request PCIe IO resource failed\n");
73 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
78 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
79 "PCIe %d MEM", pp->index);
80 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
81 pp->res[1].name = pp->mem_space_name;
83 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
84 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
86 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
87 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
89 pp->res[1].flags = IORESOURCE_MEM;
90 if (request_resource(&iomem_resource, &pp->res[1]))
91 panic("Request PCIe Memory resource failed\n");
92 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
97 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
100 * Don't go out when trying to access nonexisting devices
103 if (bus == pp->root_bus_nr && dev > 1)
109 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
112 struct pci_sys_data *sys = bus->sysdata;
113 struct pcie_port *pp = sys->private_data;
117 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
119 return PCIBIOS_DEVICE_NOT_FOUND;
122 spin_lock_irqsave(&pp->conf_lock, flags);
123 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
124 spin_unlock_irqrestore(&pp->conf_lock, flags);
129 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
130 int where, int size, u32 val)
132 struct pci_sys_data *sys = bus->sysdata;
133 struct pcie_port *pp = sys->private_data;
137 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
138 return PCIBIOS_DEVICE_NOT_FOUND;
140 spin_lock_irqsave(&pp->conf_lock, flags);
141 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
142 spin_unlock_irqrestore(&pp->conf_lock, flags);
147 static struct pci_ops pcie_ops = {
148 .read = pcie_rd_conf,
149 .write = pcie_wr_conf,
152 static void __devinit rc_pci_fixup(struct pci_dev *dev)
155 * Prevent enumeration of root complex.
157 if (dev->bus->parent == NULL && dev->devfn == 0) {
160 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
161 dev->resource[i].start = 0;
162 dev->resource[i].end = 0;
163 dev->resource[i].flags = 0;
167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
169 static struct pci_bus __init *
170 dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
174 if (nr < num_pcie_ports) {
175 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
185 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
187 struct pci_sys_data *sys = dev->sysdata;
188 struct pcie_port *pp = sys->private_data;
190 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
193 static struct hw_pci dove_pci __initdata = {
195 .setup = dove_pcie_setup,
196 .scan = dove_pcie_scan_bus,
197 .map_irq = dove_pcie_map_irq,
200 static void __init add_pcie_port(int index, unsigned long base)
202 printk(KERN_INFO "Dove PCIe port %d: ", index);
204 if (orion_pcie_link_up((void __iomem *)base)) {
205 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
207 printk(KERN_INFO "link up\n");
210 pp->root_bus_nr = -1;
211 pp->base = (void __iomem *)base;
212 spin_lock_init(&pp->conf_lock);
213 memset(pp->res, 0, sizeof(pp->res));
215 printk(KERN_INFO "link down, ignoring\n");
219 void __init dove_pcie_init(int init_port0, int init_port1)
221 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
224 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
227 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
229 pci_common_init(&dove_pci);