2 * linux/arch/arm/mach-ebsa110/isamem.c
4 * Copyright (C) 2001 Russell King
6 * Perform "ISA" memory and IO accesses. The EBSA110 has some "peculiarities"
7 * in the way it handles accesses to odd IO ports on 16-bit devices. These
8 * devices have their D0-D15 lines connected to the processors D0-D15 lines.
9 * Since they expect all byte IO operations to be performed on D0-D7, and the
10 * StrongARM expects to transfer the byte to these odd addresses on D8-D15,
11 * we must use a trick to get the required behaviour.
13 * The trick employed here is to use long word stores to odd address -1. The
14 * glue logic picks this up as a "trick" access, and asserts the LSB of the
15 * peripherals address bus, thereby accessing the odd IO port. Meanwhile, the
16 * StrongARM transfers its data on D0-D7 as expected.
18 * Things get more interesting on the pass-1 EBSA110 - the PCMCIA controller
19 * wiring was screwed in such a way that it had limited memory space access.
20 * Luckily, the work-around for this is not too horrible. See
21 * __isamem_convert_addr for the details.
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/types.h>
28 #include <mach/hardware.h>
31 static void __iomem *__isamem_convert_addr(const volatile void __iomem *addr)
33 u32 ret, a = (u32 __force) addr;
36 * The PCMCIA controller is wired up as follows:
37 * +---------+---------+---------+---------+---------+---------+
38 * PCMCIA | 2 2 2 2 | 1 1 1 1 | 1 1 1 1 | 1 1 | | |
39 * | 3 2 1 0 | 9 8 7 6 | 5 4 3 2 | 1 0 9 8 | 7 6 5 4 | 3 2 1 0 |
40 * +---------+---------+---------+---------+---------+---------+
41 * CPU | 2 2 2 2 | 2 1 1 1 | 1 1 1 1 | 1 1 1 | | |
42 * | 4 3 2 1 | 0 9 9 8 | 7 6 5 4 | 3 2 0 9 | 8 7 6 5 | 4 3 2 x |
43 * +---------+---------+---------+---------+---------+---------+
45 * This means that we can access PCMCIA regions as follows:
46 * 0x*10000 -> 0x*1ffff
47 * 0x*70000 -> 0x*7ffff
48 * 0x*90000 -> 0x*9ffff
49 * 0x*f0000 -> 0x*fffff
51 ret = (a & 0xf803fe) << 1;
52 ret |= (a & 0x03fc00) << 2;
56 if ((a & 0x20000) == (a & 0x40000) >> 1)
57 return (void __iomem *)ret;
64 * read[bwl] and write[bwl]
66 u8 __readb(const volatile void __iomem *addr)
68 void __iomem *a = __isamem_convert_addr(addr);
71 if ((unsigned long)addr & 1)
78 u16 __readw(const volatile void __iomem *addr)
80 void __iomem *a = __isamem_convert_addr(addr);
82 if ((unsigned long)addr & 1)
85 return __raw_readw(a);
88 u32 __readl(const volatile void __iomem *addr)
90 void __iomem *a = __isamem_convert_addr(addr);
93 if ((unsigned long)addr & 3)
97 ret |= __raw_readw(a + 4) << 16;
101 EXPORT_SYMBOL(__readb);
102 EXPORT_SYMBOL(__readw);
103 EXPORT_SYMBOL(__readl);
105 void readsw(const volatile void __iomem *addr, void *data, int len)
107 void __iomem *a = __isamem_convert_addr(addr);
109 BUG_ON((unsigned long)addr & 1);
111 __raw_readsw(a, data, len);
113 EXPORT_SYMBOL(readsw);
115 void readsl(const volatile void __iomem *addr, void *data, int len)
117 void __iomem *a = __isamem_convert_addr(addr);
119 BUG_ON((unsigned long)addr & 3);
121 __raw_readsl(a, data, len);
123 EXPORT_SYMBOL(readsl);
125 void __writeb(u8 val, volatile void __iomem *addr)
127 void __iomem *a = __isamem_convert_addr(addr);
129 if ((unsigned long)addr & 1)
130 __raw_writel(val, a);
132 __raw_writeb(val, a);
135 void __writew(u16 val, volatile void __iomem *addr)
137 void __iomem *a = __isamem_convert_addr(addr);
139 if ((unsigned long)addr & 1)
142 __raw_writew(val, a);
145 void __writel(u32 val, volatile void __iomem *addr)
147 void __iomem *a = __isamem_convert_addr(addr);
149 if ((unsigned long)addr & 3)
152 __raw_writew(val, a);
153 __raw_writew(val >> 16, a + 4);
156 EXPORT_SYMBOL(__writeb);
157 EXPORT_SYMBOL(__writew);
158 EXPORT_SYMBOL(__writel);
160 void writesw(volatile void __iomem *addr, const void *data, int len)
162 void __iomem *a = __isamem_convert_addr(addr);
164 BUG_ON((unsigned long)addr & 1);
166 __raw_writesw(a, data, len);
168 EXPORT_SYMBOL(writesw);
170 void writesl(volatile void __iomem *addr, const void *data, int len)
172 void __iomem *a = __isamem_convert_addr(addr);
174 BUG_ON((unsigned long)addr & 3);
176 __raw_writesl(a, data, len);
178 EXPORT_SYMBOL(writesl);
181 * The EBSA110 has a weird "ISA IO" region:
183 * Region 0 (addr = 0xf0000000 + io << 2)
184 * --------------------------------------------------------
185 * Physical region IO region
186 * f0000fe0 - f0000ffc 3f8 - 3ff ttyS0
187 * f0000e60 - f0000e64 398 - 399
188 * f0000de0 - f0000dfc 378 - 37f lp0
189 * f0000be0 - f0000bfc 2f8 - 2ff ttyS1
191 * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
192 * --------------------------------------------------------
193 * Physical region IO region
194 * f00014f1 a79 pnp write data
195 * f00007c0 - f00007c1 3e0 - 3e1 pcmcia
196 * f00004f1 279 pnp address
197 * f0000440 - f000046c 220 - 236 eth0
198 * f0000405 203 pnp read data
200 #define SUPERIO_PORT(p) \
201 (((p) >> 3) == (0x3f8 >> 3) || \
202 ((p) >> 3) == (0x2f8 >> 3) || \
203 ((p) >> 3) == (0x378 >> 3))
206 * We're addressing an 8 or 16-bit peripheral which tranfers
207 * odd addresses on the low ISA byte lane.
209 u8 __inb8(unsigned int port)
214 * The SuperIO registers use sane addressing techniques...
216 if (SUPERIO_PORT(port))
217 ret = __raw_readb((void __iomem *)ISAIO_BASE + (port << 2));
219 void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
222 * Shame nothing else does
225 ret = __raw_readl(a);
227 ret = __raw_readb(a);
233 * We're addressing a 16-bit peripheral which transfers odd
234 * addresses on the high ISA byte lane.
236 u8 __inb16(unsigned int port)
241 * The SuperIO registers use sane addressing techniques...
243 if (SUPERIO_PORT(port))
246 offset = (port & ~1) << 1 | (port & 1);
248 return __raw_readb((void __iomem *)ISAIO_BASE + offset);
251 u16 __inw(unsigned int port)
256 * The SuperIO registers use sane addressing techniques...
258 if (SUPERIO_PORT(port))
264 return __raw_readw((void __iomem *)ISAIO_BASE + offset);
268 * Fake a 32-bit read with two 16-bit reads. Needed for 3c589.
270 u32 __inl(unsigned int port)
274 if (SUPERIO_PORT(port) || port & 3)
277 a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
279 return __raw_readw(a) | __raw_readw(a + 4) << 16;
282 EXPORT_SYMBOL(__inb8);
283 EXPORT_SYMBOL(__inb16);
284 EXPORT_SYMBOL(__inw);
285 EXPORT_SYMBOL(__inl);
287 void __outb8(u8 val, unsigned int port)
290 * The SuperIO registers use sane addressing techniques...
292 if (SUPERIO_PORT(port))
293 __raw_writeb(val, (void __iomem *)ISAIO_BASE + (port << 2));
295 void __iomem *a = (void __iomem *)ISAIO_BASE + ((port & ~1) << 1);
298 * Shame nothing else does
301 __raw_writel(val, a);
303 __raw_writeb(val, a);
307 void __outb16(u8 val, unsigned int port)
312 * The SuperIO registers use sane addressing techniques...
314 if (SUPERIO_PORT(port))
317 offset = (port & ~1) << 1 | (port & 1);
319 __raw_writeb(val, (void __iomem *)ISAIO_BASE + offset);
322 void __outw(u16 val, unsigned int port)
327 * The SuperIO registers use sane addressing techniques...
329 if (SUPERIO_PORT(port))
335 __raw_writew(val, (void __iomem *)ISAIO_BASE + offset);
338 void __outl(u32 val, unsigned int port)
343 EXPORT_SYMBOL(__outb8);
344 EXPORT_SYMBOL(__outb16);
345 EXPORT_SYMBOL(__outw);
346 EXPORT_SYMBOL(__outl);
348 void outsb(unsigned int port, const void *from, int len)
352 if (SUPERIO_PORT(port))
355 off = (port & ~1) << 1;
360 __raw_writesb((void __iomem *)ISAIO_BASE + off, from, len);
363 void insb(unsigned int port, void *from, int len)
367 if (SUPERIO_PORT(port))
370 off = (port & ~1) << 1;
375 __raw_readsb((void __iomem *)ISAIO_BASE + off, from, len);
378 EXPORT_SYMBOL(outsb);
381 void outsw(unsigned int port, const void *from, int len)
385 if (SUPERIO_PORT(port))
388 off = (port & ~1) << 1;
393 __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len);
396 void insw(unsigned int port, void *from, int len)
400 if (SUPERIO_PORT(port))
403 off = (port & ~1) << 1;
408 __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len);
411 EXPORT_SYMBOL(outsw);
415 * We implement these as 16-bit insw/outsw, mainly for
418 void outsl(unsigned int port, const void *from, int len)
422 if (SUPERIO_PORT(port) || port & 3)
425 __raw_writesw((void __iomem *)ISAIO_BASE + off, from, len << 1);
428 void insl(unsigned int port, void *from, int len)
432 if (SUPERIO_PORT(port) || port & 3)
435 __raw_readsw((void __iomem *)ISAIO_BASE + off, from, len << 1);
438 EXPORT_SYMBOL(outsl);