2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
29 #include "clock-exynos4.h"
31 #ifdef CONFIG_PM_SLEEP
32 static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
34 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
39 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
40 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
41 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
42 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
43 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
44 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
45 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
46 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
48 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
49 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
50 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
51 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
52 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
53 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
54 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
58 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
64 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
65 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
74 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
75 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
83 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
84 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
85 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
86 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
88 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
89 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
90 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
93 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
97 static struct clk exynos4_clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m",
102 static struct clk exynos4_clk_sclk_hdmiphy = {
103 .name = "sclk_hdmiphy",
106 static struct clk exynos4_clk_sclk_usbphy0 = {
107 .name = "sclk_usbphy0",
111 static struct clk exynos4_clk_sclk_usbphy1 = {
112 .name = "sclk_usbphy1",
115 static struct clk dummy_apb_pclk = {
120 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
125 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
130 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
135 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
140 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
145 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
150 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
155 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
160 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
165 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
170 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
175 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
180 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
185 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
190 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
195 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
200 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
202 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
205 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
207 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
210 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
212 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
215 /* Core list of CMU_CPU side */
217 static struct clksrc_clk exynos4_clk_mout_apll = {
221 .sources = &clk_src_apll,
222 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
225 static struct clksrc_clk exynos4_clk_sclk_apll = {
228 .parent = &exynos4_clk_mout_apll.clk,
230 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
233 static struct clksrc_clk exynos4_clk_mout_epll = {
237 .sources = &clk_src_epll,
238 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
241 struct clksrc_clk exynos4_clk_mout_mpll = {
245 .sources = &clk_src_mpll,
247 /* reg_src will be added in each SoCs' clock */
250 static struct clk *exynos4_clkset_moutcore_list[] = {
251 [0] = &exynos4_clk_mout_apll.clk,
252 [1] = &exynos4_clk_mout_mpll.clk,
255 static struct clksrc_sources exynos4_clkset_moutcore = {
256 .sources = exynos4_clkset_moutcore_list,
257 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
260 static struct clksrc_clk exynos4_clk_moutcore = {
264 .sources = &exynos4_clkset_moutcore,
265 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
268 static struct clksrc_clk exynos4_clk_coreclk = {
271 .parent = &exynos4_clk_moutcore.clk,
273 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
276 static struct clksrc_clk exynos4_clk_armclk = {
279 .parent = &exynos4_clk_coreclk.clk,
283 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
285 .name = "aclk_corem0",
286 .parent = &exynos4_clk_coreclk.clk,
288 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
291 static struct clksrc_clk exynos4_clk_aclk_cores = {
293 .name = "aclk_cores",
294 .parent = &exynos4_clk_coreclk.clk,
296 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
299 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
301 .name = "aclk_corem1",
302 .parent = &exynos4_clk_coreclk.clk,
304 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
307 static struct clksrc_clk exynos4_clk_periphclk = {
310 .parent = &exynos4_clk_coreclk.clk,
312 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
315 /* Core list of CMU_CORE side */
317 static struct clk *exynos4_clkset_corebus_list[] = {
318 [0] = &exynos4_clk_mout_mpll.clk,
319 [1] = &exynos4_clk_sclk_apll.clk,
322 struct clksrc_sources exynos4_clkset_mout_corebus = {
323 .sources = exynos4_clkset_corebus_list,
324 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
327 static struct clksrc_clk exynos4_clk_mout_corebus = {
329 .name = "mout_corebus",
331 .sources = &exynos4_clkset_mout_corebus,
332 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
335 static struct clksrc_clk exynos4_clk_sclk_dmc = {
338 .parent = &exynos4_clk_mout_corebus.clk,
340 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
343 static struct clksrc_clk exynos4_clk_aclk_cored = {
345 .name = "aclk_cored",
346 .parent = &exynos4_clk_sclk_dmc.clk,
348 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
351 static struct clksrc_clk exynos4_clk_aclk_corep = {
353 .name = "aclk_corep",
354 .parent = &exynos4_clk_aclk_cored.clk,
356 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
359 static struct clksrc_clk exynos4_clk_aclk_acp = {
362 .parent = &exynos4_clk_mout_corebus.clk,
364 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
367 static struct clksrc_clk exynos4_clk_pclk_acp = {
370 .parent = &exynos4_clk_aclk_acp.clk,
372 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
375 /* Core list of CMU_TOP side */
377 struct clk *exynos4_clkset_aclk_top_list[] = {
378 [0] = &exynos4_clk_mout_mpll.clk,
379 [1] = &exynos4_clk_sclk_apll.clk,
382 static struct clksrc_sources exynos4_clkset_aclk = {
383 .sources = exynos4_clkset_aclk_top_list,
384 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
387 static struct clksrc_clk exynos4_clk_aclk_200 = {
391 .sources = &exynos4_clkset_aclk,
392 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
393 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
396 static struct clksrc_clk exynos4_clk_aclk_100 = {
400 .sources = &exynos4_clkset_aclk,
401 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
402 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
405 static struct clksrc_clk exynos4_clk_aclk_160 = {
409 .sources = &exynos4_clkset_aclk,
410 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
411 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
414 struct clksrc_clk exynos4_clk_aclk_133 = {
418 .sources = &exynos4_clkset_aclk,
419 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
420 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
423 static struct clk *exynos4_clkset_vpllsrc_list[] = {
425 [1] = &exynos4_clk_sclk_hdmi27m,
428 static struct clksrc_sources exynos4_clkset_vpllsrc = {
429 .sources = exynos4_clkset_vpllsrc_list,
430 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
433 static struct clksrc_clk exynos4_clk_vpllsrc = {
436 .enable = exynos4_clksrc_mask_top_ctrl,
439 .sources = &exynos4_clkset_vpllsrc,
440 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
443 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
444 [0] = &exynos4_clk_vpllsrc.clk,
445 [1] = &clk_fout_vpll,
448 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
449 .sources = exynos4_clkset_sclk_vpll_list,
450 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
453 static struct clksrc_clk exynos4_clk_sclk_vpll = {
457 .sources = &exynos4_clkset_sclk_vpll,
458 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
461 static struct clk exynos4_init_clocks_off[] = {
464 .parent = &exynos4_clk_aclk_100.clk,
465 .enable = exynos4_clk_ip_peril_ctrl,
469 .devname = "s5p-mipi-csis.0",
470 .enable = exynos4_clk_ip_cam_ctrl,
474 .devname = "s5p-mipi-csis.1",
475 .enable = exynos4_clk_ip_cam_ctrl,
480 .enable = exynos4_clk_ip_cam_ctrl,
484 .devname = "exynos4-fimc.0",
485 .enable = exynos4_clk_ip_cam_ctrl,
489 .devname = "exynos4-fimc.1",
490 .enable = exynos4_clk_ip_cam_ctrl,
494 .devname = "exynos4-fimc.2",
495 .enable = exynos4_clk_ip_cam_ctrl,
499 .devname = "exynos4-fimc.3",
500 .enable = exynos4_clk_ip_cam_ctrl,
504 .enable = exynos4_clk_ip_fsys_ctrl,
508 .devname = "exynos4-sdhci.0",
509 .parent = &exynos4_clk_aclk_133.clk,
510 .enable = exynos4_clk_ip_fsys_ctrl,
514 .devname = "exynos4-sdhci.1",
515 .parent = &exynos4_clk_aclk_133.clk,
516 .enable = exynos4_clk_ip_fsys_ctrl,
520 .devname = "exynos4-sdhci.2",
521 .parent = &exynos4_clk_aclk_133.clk,
522 .enable = exynos4_clk_ip_fsys_ctrl,
526 .devname = "exynos4-sdhci.3",
527 .parent = &exynos4_clk_aclk_133.clk,
528 .enable = exynos4_clk_ip_fsys_ctrl,
532 .parent = &exynos4_clk_aclk_133.clk,
533 .enable = exynos4_clk_ip_fsys_ctrl,
537 .enable = exynos4_clk_ip_fsys_ctrl,
538 .ctrlbit = (1 << 15),
541 .enable = exynos4_clk_ip_fsys_ctrl,
542 .ctrlbit = (1 << 16),
545 .devname = "s5p-sdo",
546 .enable = exynos4_clk_ip_tv_ctrl,
550 .devname = "s5p-mixer",
551 .enable = exynos4_clk_ip_tv_ctrl,
555 .devname = "s5p-mixer",
556 .enable = exynos4_clk_ip_tv_ctrl,
560 .devname = "exynos4-hdmi",
561 .enable = exynos4_clk_ip_tv_ctrl,
565 .devname = "exynos4-hdmi",
566 .enable = exynos4_clk_hdmiphy_ctrl,
570 .devname = "s5p-sdo",
571 .enable = exynos4_clk_dac_ctrl,
575 .enable = exynos4_clk_ip_peril_ctrl,
576 .ctrlbit = (1 << 15),
579 .enable = exynos4_clk_ip_perir_ctrl,
580 .ctrlbit = (1 << 17),
583 .enable = exynos4_clk_ip_perir_ctrl,
584 .ctrlbit = (1 << 16),
587 .enable = exynos4_clk_ip_perir_ctrl,
588 .ctrlbit = (1 << 15),
591 .parent = &exynos4_clk_aclk_100.clk,
592 .enable = exynos4_clk_ip_perir_ctrl,
593 .ctrlbit = (1 << 14),
596 .enable = exynos4_clk_ip_fsys_ctrl ,
597 .ctrlbit = (1 << 12),
600 .enable = exynos4_clk_ip_fsys_ctrl,
601 .ctrlbit = (1 << 13),
604 .devname = "exynos4210-spi.0",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 16),
609 .devname = "exynos4210-spi.1",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 17),
614 .devname = "exynos4210-spi.2",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 18),
619 .devname = "samsung-i2s.1",
620 .enable = exynos4_clk_ip_peril_ctrl,
621 .ctrlbit = (1 << 20),
624 .devname = "samsung-i2s.2",
625 .enable = exynos4_clk_ip_peril_ctrl,
626 .ctrlbit = (1 << 21),
629 .devname = "samsung-pcm.1",
630 .enable = exynos4_clk_ip_peril_ctrl,
631 .ctrlbit = (1 << 22),
634 .devname = "samsung-pcm.2",
635 .enable = exynos4_clk_ip_peril_ctrl,
636 .ctrlbit = (1 << 23),
639 .enable = exynos4_clk_ip_peril_ctrl,
640 .ctrlbit = (1 << 25),
643 .devname = "samsung-spdif",
644 .enable = exynos4_clk_ip_peril_ctrl,
645 .ctrlbit = (1 << 26),
648 .devname = "samsung-ac97",
649 .enable = exynos4_clk_ip_peril_ctrl,
650 .ctrlbit = (1 << 27),
653 .devname = "s5p-mfc",
654 .enable = exynos4_clk_ip_mfc_ctrl,
658 .devname = "s3c2440-i2c.0",
659 .parent = &exynos4_clk_aclk_100.clk,
660 .enable = exynos4_clk_ip_peril_ctrl,
664 .devname = "s3c2440-i2c.1",
665 .parent = &exynos4_clk_aclk_100.clk,
666 .enable = exynos4_clk_ip_peril_ctrl,
670 .devname = "s3c2440-i2c.2",
671 .parent = &exynos4_clk_aclk_100.clk,
672 .enable = exynos4_clk_ip_peril_ctrl,
676 .devname = "s3c2440-i2c.3",
677 .parent = &exynos4_clk_aclk_100.clk,
678 .enable = exynos4_clk_ip_peril_ctrl,
682 .devname = "s3c2440-i2c.4",
683 .parent = &exynos4_clk_aclk_100.clk,
684 .enable = exynos4_clk_ip_peril_ctrl,
685 .ctrlbit = (1 << 10),
688 .devname = "s3c2440-i2c.5",
689 .parent = &exynos4_clk_aclk_100.clk,
690 .enable = exynos4_clk_ip_peril_ctrl,
691 .ctrlbit = (1 << 11),
694 .devname = "s3c2440-i2c.6",
695 .parent = &exynos4_clk_aclk_100.clk,
696 .enable = exynos4_clk_ip_peril_ctrl,
697 .ctrlbit = (1 << 12),
700 .devname = "s3c2440-i2c.7",
701 .parent = &exynos4_clk_aclk_100.clk,
702 .enable = exynos4_clk_ip_peril_ctrl,
703 .ctrlbit = (1 << 13),
706 .devname = "s3c2440-hdmiphy-i2c",
707 .parent = &exynos4_clk_aclk_100.clk,
708 .enable = exynos4_clk_ip_peril_ctrl,
709 .ctrlbit = (1 << 14),
712 .devname = "exynos-sysmmu.0",
713 .enable = exynos4_clk_ip_mfc_ctrl,
717 .devname = "exynos-sysmmu.1",
718 .enable = exynos4_clk_ip_mfc_ctrl,
722 .devname = "exynos-sysmmu.2",
723 .enable = exynos4_clk_ip_tv_ctrl,
727 .devname = "exynos-sysmmu.3",
728 .enable = exynos4_clk_ip_cam_ctrl,
729 .ctrlbit = (1 << 11),
732 .devname = "exynos-sysmmu.4",
733 .enable = exynos4_clk_ip_image_ctrl,
737 .devname = "exynos-sysmmu.5",
738 .enable = exynos4_clk_ip_cam_ctrl,
742 .devname = "exynos-sysmmu.6",
743 .enable = exynos4_clk_ip_cam_ctrl,
747 .devname = "exynos-sysmmu.7",
748 .enable = exynos4_clk_ip_cam_ctrl,
752 .devname = "exynos-sysmmu.8",
753 .enable = exynos4_clk_ip_cam_ctrl,
754 .ctrlbit = (1 << 10),
757 .devname = "exynos-sysmmu.10",
758 .enable = exynos4_clk_ip_lcd0_ctrl,
763 static struct clk exynos4_init_clocks_on[] = {
766 .devname = "s5pv210-uart.0",
767 .enable = exynos4_clk_ip_peril_ctrl,
771 .devname = "s5pv210-uart.1",
772 .enable = exynos4_clk_ip_peril_ctrl,
776 .devname = "s5pv210-uart.2",
777 .enable = exynos4_clk_ip_peril_ctrl,
781 .devname = "s5pv210-uart.3",
782 .enable = exynos4_clk_ip_peril_ctrl,
786 .devname = "s5pv210-uart.4",
787 .enable = exynos4_clk_ip_peril_ctrl,
791 .devname = "s5pv210-uart.5",
792 .enable = exynos4_clk_ip_peril_ctrl,
797 static struct clk exynos4_clk_pdma0 = {
799 .devname = "dma-pl330.0",
800 .enable = exynos4_clk_ip_fsys_ctrl,
804 static struct clk exynos4_clk_pdma1 = {
806 .devname = "dma-pl330.1",
807 .enable = exynos4_clk_ip_fsys_ctrl,
811 static struct clk exynos4_clk_mdma1 = {
813 .devname = "dma-pl330.2",
814 .enable = exynos4_clk_ip_image_ctrl,
815 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
818 static struct clk exynos4_clk_fimd0 = {
820 .devname = "exynos4-fb.0",
821 .enable = exynos4_clk_ip_lcd0_ctrl,
825 struct clk *exynos4_clkset_group_list[] = {
826 [0] = &clk_ext_xtal_mux,
828 [2] = &exynos4_clk_sclk_hdmi27m,
829 [3] = &exynos4_clk_sclk_usbphy0,
830 [4] = &exynos4_clk_sclk_usbphy1,
831 [5] = &exynos4_clk_sclk_hdmiphy,
832 [6] = &exynos4_clk_mout_mpll.clk,
833 [7] = &exynos4_clk_mout_epll.clk,
834 [8] = &exynos4_clk_sclk_vpll.clk,
837 struct clksrc_sources exynos4_clkset_group = {
838 .sources = exynos4_clkset_group_list,
839 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
842 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
843 [0] = &exynos4_clk_mout_mpll.clk,
844 [1] = &exynos4_clk_sclk_apll.clk,
847 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
848 .sources = exynos4_clkset_mout_g2d0_list,
849 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
852 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
853 [0] = &exynos4_clk_mout_epll.clk,
854 [1] = &exynos4_clk_sclk_vpll.clk,
857 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
858 .sources = exynos4_clkset_mout_g2d1_list,
859 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
862 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
863 [0] = &exynos4_clk_mout_mpll.clk,
864 [1] = &exynos4_clk_sclk_apll.clk,
867 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
868 .sources = exynos4_clkset_mout_mfc0_list,
869 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
872 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
876 .sources = &exynos4_clkset_mout_mfc0,
877 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
880 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
881 [0] = &exynos4_clk_mout_epll.clk,
882 [1] = &exynos4_clk_sclk_vpll.clk,
885 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
886 .sources = exynos4_clkset_mout_mfc1_list,
887 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
890 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
894 .sources = &exynos4_clkset_mout_mfc1,
895 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
898 static struct clk *exynos4_clkset_mout_mfc_list[] = {
899 [0] = &exynos4_clk_mout_mfc0.clk,
900 [1] = &exynos4_clk_mout_mfc1.clk,
903 static struct clksrc_sources exynos4_clkset_mout_mfc = {
904 .sources = exynos4_clkset_mout_mfc_list,
905 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
908 static struct clk *exynos4_clkset_sclk_dac_list[] = {
909 [0] = &exynos4_clk_sclk_vpll.clk,
910 [1] = &exynos4_clk_sclk_hdmiphy,
913 static struct clksrc_sources exynos4_clkset_sclk_dac = {
914 .sources = exynos4_clkset_sclk_dac_list,
915 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
918 static struct clksrc_clk exynos4_clk_sclk_dac = {
921 .enable = exynos4_clksrc_mask_tv_ctrl,
924 .sources = &exynos4_clkset_sclk_dac,
925 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
928 static struct clksrc_clk exynos4_clk_sclk_pixel = {
930 .name = "sclk_pixel",
931 .parent = &exynos4_clk_sclk_vpll.clk,
933 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
936 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
937 [0] = &exynos4_clk_sclk_pixel.clk,
938 [1] = &exynos4_clk_sclk_hdmiphy,
941 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
942 .sources = exynos4_clkset_sclk_hdmi_list,
943 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
946 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
949 .enable = exynos4_clksrc_mask_tv_ctrl,
952 .sources = &exynos4_clkset_sclk_hdmi,
953 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
956 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
957 [0] = &exynos4_clk_sclk_dac.clk,
958 [1] = &exynos4_clk_sclk_hdmi.clk,
961 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
962 .sources = exynos4_clkset_sclk_mixer_list,
963 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
966 static struct clksrc_clk exynos4_clk_sclk_mixer = {
968 .name = "sclk_mixer",
969 .enable = exynos4_clksrc_mask_tv_ctrl,
972 .sources = &exynos4_clkset_sclk_mixer,
973 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
976 static struct clksrc_clk *exynos4_sclk_tv[] = {
977 &exynos4_clk_sclk_dac,
978 &exynos4_clk_sclk_pixel,
979 &exynos4_clk_sclk_hdmi,
980 &exynos4_clk_sclk_mixer,
983 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
987 .sources = &exynos4_clkset_group,
988 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
989 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
992 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
996 .sources = &exynos4_clkset_group,
997 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
998 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1001 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1003 .name = "dout_mmc2",
1005 .sources = &exynos4_clkset_group,
1006 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1007 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1010 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1012 .name = "dout_mmc3",
1014 .sources = &exynos4_clkset_group,
1015 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1016 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1019 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1021 .name = "dout_mmc4",
1023 .sources = &exynos4_clkset_group,
1024 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1025 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1028 static struct clksrc_clk exynos4_clksrcs[] = {
1032 .enable = exynos4_clksrc_mask_peril0_ctrl,
1033 .ctrlbit = (1 << 24),
1035 .sources = &exynos4_clkset_group,
1036 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1037 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1040 .name = "sclk_csis",
1041 .devname = "s5p-mipi-csis.0",
1042 .enable = exynos4_clksrc_mask_cam_ctrl,
1043 .ctrlbit = (1 << 24),
1045 .sources = &exynos4_clkset_group,
1046 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1047 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1050 .name = "sclk_csis",
1051 .devname = "s5p-mipi-csis.1",
1052 .enable = exynos4_clksrc_mask_cam_ctrl,
1053 .ctrlbit = (1 << 28),
1055 .sources = &exynos4_clkset_group,
1056 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1057 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1060 .name = "sclk_cam0",
1061 .enable = exynos4_clksrc_mask_cam_ctrl,
1062 .ctrlbit = (1 << 16),
1064 .sources = &exynos4_clkset_group,
1065 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1066 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1069 .name = "sclk_cam1",
1070 .enable = exynos4_clksrc_mask_cam_ctrl,
1071 .ctrlbit = (1 << 20),
1073 .sources = &exynos4_clkset_group,
1074 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1075 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1078 .name = "sclk_fimc",
1079 .devname = "exynos4-fimc.0",
1080 .enable = exynos4_clksrc_mask_cam_ctrl,
1081 .ctrlbit = (1 << 0),
1083 .sources = &exynos4_clkset_group,
1084 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1085 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1088 .name = "sclk_fimc",
1089 .devname = "exynos4-fimc.1",
1090 .enable = exynos4_clksrc_mask_cam_ctrl,
1091 .ctrlbit = (1 << 4),
1093 .sources = &exynos4_clkset_group,
1094 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1095 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1098 .name = "sclk_fimc",
1099 .devname = "exynos4-fimc.2",
1100 .enable = exynos4_clksrc_mask_cam_ctrl,
1101 .ctrlbit = (1 << 8),
1103 .sources = &exynos4_clkset_group,
1104 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1105 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1108 .name = "sclk_fimc",
1109 .devname = "exynos4-fimc.3",
1110 .enable = exynos4_clksrc_mask_cam_ctrl,
1111 .ctrlbit = (1 << 12),
1113 .sources = &exynos4_clkset_group,
1114 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1115 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1118 .name = "sclk_fimd",
1119 .devname = "exynos4-fb.0",
1120 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1121 .ctrlbit = (1 << 0),
1123 .sources = &exynos4_clkset_group,
1124 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1125 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1129 .devname = "s5p-mfc",
1131 .sources = &exynos4_clkset_mout_mfc,
1132 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1133 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1137 .parent = &exynos4_clk_dout_mmc4.clk,
1138 .enable = exynos4_clksrc_mask_fsys_ctrl,
1139 .ctrlbit = (1 << 16),
1141 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1145 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1148 .devname = "exynos4210-uart.0",
1149 .enable = exynos4_clksrc_mask_peril0_ctrl,
1150 .ctrlbit = (1 << 0),
1152 .sources = &exynos4_clkset_group,
1153 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1154 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1157 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1160 .devname = "exynos4210-uart.1",
1161 .enable = exynos4_clksrc_mask_peril0_ctrl,
1162 .ctrlbit = (1 << 4),
1164 .sources = &exynos4_clkset_group,
1165 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1166 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1169 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1172 .devname = "exynos4210-uart.2",
1173 .enable = exynos4_clksrc_mask_peril0_ctrl,
1174 .ctrlbit = (1 << 8),
1176 .sources = &exynos4_clkset_group,
1177 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1178 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1181 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1184 .devname = "exynos4210-uart.3",
1185 .enable = exynos4_clksrc_mask_peril0_ctrl,
1186 .ctrlbit = (1 << 12),
1188 .sources = &exynos4_clkset_group,
1189 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1190 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1193 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1196 .devname = "exynos4-sdhci.0",
1197 .parent = &exynos4_clk_dout_mmc0.clk,
1198 .enable = exynos4_clksrc_mask_fsys_ctrl,
1199 .ctrlbit = (1 << 0),
1201 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1204 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1207 .devname = "exynos4-sdhci.1",
1208 .parent = &exynos4_clk_dout_mmc1.clk,
1209 .enable = exynos4_clksrc_mask_fsys_ctrl,
1210 .ctrlbit = (1 << 4),
1212 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1215 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1218 .devname = "exynos4-sdhci.2",
1219 .parent = &exynos4_clk_dout_mmc2.clk,
1220 .enable = exynos4_clksrc_mask_fsys_ctrl,
1221 .ctrlbit = (1 << 8),
1223 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1226 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1229 .devname = "exynos4-sdhci.3",
1230 .parent = &exynos4_clk_dout_mmc3.clk,
1231 .enable = exynos4_clksrc_mask_fsys_ctrl,
1232 .ctrlbit = (1 << 12),
1234 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1237 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1239 .name = "mdout_spi",
1240 .devname = "exynos4210-spi.0",
1242 .sources = &exynos4_clkset_group,
1243 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1244 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1247 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1249 .name = "mdout_spi",
1250 .devname = "exynos4210-spi.1",
1252 .sources = &exynos4_clkset_group,
1253 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1254 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1257 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1259 .name = "mdout_spi",
1260 .devname = "exynos4210-spi.2",
1262 .sources = &exynos4_clkset_group,
1263 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1267 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1270 .devname = "exynos4210-spi.0",
1271 .parent = &exynos4_clk_mdout_spi0.clk,
1272 .enable = exynos4_clksrc_mask_peril1_ctrl,
1273 .ctrlbit = (1 << 16),
1275 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1278 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1281 .devname = "exynos4210-spi.1",
1282 .parent = &exynos4_clk_mdout_spi1.clk,
1283 .enable = exynos4_clksrc_mask_peril1_ctrl,
1284 .ctrlbit = (1 << 20),
1286 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1289 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1292 .devname = "exynos4210-spi.2",
1293 .parent = &exynos4_clk_mdout_spi2.clk,
1294 .enable = exynos4_clksrc_mask_peril1_ctrl,
1295 .ctrlbit = (1 << 24),
1297 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1300 /* Clock initialization code */
1301 static struct clksrc_clk *exynos4_sysclks[] = {
1302 &exynos4_clk_mout_apll,
1303 &exynos4_clk_sclk_apll,
1304 &exynos4_clk_mout_epll,
1305 &exynos4_clk_mout_mpll,
1306 &exynos4_clk_moutcore,
1307 &exynos4_clk_coreclk,
1308 &exynos4_clk_armclk,
1309 &exynos4_clk_aclk_corem0,
1310 &exynos4_clk_aclk_cores,
1311 &exynos4_clk_aclk_corem1,
1312 &exynos4_clk_periphclk,
1313 &exynos4_clk_mout_corebus,
1314 &exynos4_clk_sclk_dmc,
1315 &exynos4_clk_aclk_cored,
1316 &exynos4_clk_aclk_corep,
1317 &exynos4_clk_aclk_acp,
1318 &exynos4_clk_pclk_acp,
1319 &exynos4_clk_vpllsrc,
1320 &exynos4_clk_sclk_vpll,
1321 &exynos4_clk_aclk_200,
1322 &exynos4_clk_aclk_100,
1323 &exynos4_clk_aclk_160,
1324 &exynos4_clk_aclk_133,
1325 &exynos4_clk_dout_mmc0,
1326 &exynos4_clk_dout_mmc1,
1327 &exynos4_clk_dout_mmc2,
1328 &exynos4_clk_dout_mmc3,
1329 &exynos4_clk_dout_mmc4,
1330 &exynos4_clk_mout_mfc0,
1331 &exynos4_clk_mout_mfc1,
1334 static struct clk *exynos4_clk_cdev[] = {
1341 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1342 &exynos4_clk_sclk_uart0,
1343 &exynos4_clk_sclk_uart1,
1344 &exynos4_clk_sclk_uart2,
1345 &exynos4_clk_sclk_uart3,
1346 &exynos4_clk_sclk_mmc0,
1347 &exynos4_clk_sclk_mmc1,
1348 &exynos4_clk_sclk_mmc2,
1349 &exynos4_clk_sclk_mmc3,
1350 &exynos4_clk_sclk_spi0,
1351 &exynos4_clk_sclk_spi1,
1352 &exynos4_clk_sclk_spi2,
1353 &exynos4_clk_mdout_spi0,
1354 &exynos4_clk_mdout_spi1,
1355 &exynos4_clk_mdout_spi2,
1358 static struct clk_lookup exynos4_clk_lookup[] = {
1359 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1360 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1361 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1362 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1363 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1364 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1365 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1366 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1367 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1368 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1369 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1370 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1371 CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1372 CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1373 CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1376 static int xtal_rate;
1378 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1380 if (soc_is_exynos4210())
1381 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1383 else if (soc_is_exynos4212() || soc_is_exynos4412())
1384 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1389 static struct clk_ops exynos4_fout_apll_ops = {
1390 .get_rate = exynos4_fout_apll_get_rate,
1393 static u32 exynos4_vpll_div[][8] = {
1394 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1395 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1398 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1403 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1405 unsigned int vpll_con0, vpll_con1 = 0;
1408 /* Return if nothing changed */
1409 if (clk->rate == rate)
1412 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1413 vpll_con0 &= ~(0x1 << 27 | \
1414 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1415 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1416 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1418 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1419 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1420 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1421 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1423 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1424 if (exynos4_vpll_div[i][0] == rate) {
1425 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1426 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1427 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1428 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1429 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1430 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1431 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1436 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1437 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1442 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1443 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1445 /* Wait for VPLL lock */
1446 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1453 static struct clk_ops exynos4_vpll_ops = {
1454 .get_rate = exynos4_vpll_get_rate,
1455 .set_rate = exynos4_vpll_set_rate,
1458 void __init_or_cpufreq exynos4_setup_clocks(void)
1460 struct clk *xtal_clk;
1461 unsigned long apll = 0;
1462 unsigned long mpll = 0;
1463 unsigned long epll = 0;
1464 unsigned long vpll = 0;
1465 unsigned long vpllsrc;
1467 unsigned long armclk;
1468 unsigned long sclk_dmc;
1469 unsigned long aclk_200;
1470 unsigned long aclk_100;
1471 unsigned long aclk_160;
1472 unsigned long aclk_133;
1475 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1477 xtal_clk = clk_get(NULL, "xtal");
1478 BUG_ON(IS_ERR(xtal_clk));
1480 xtal = clk_get_rate(xtal_clk);
1486 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1488 if (soc_is_exynos4210()) {
1489 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1491 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1493 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1494 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1496 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1497 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1498 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1499 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1500 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1501 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1502 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1503 __raw_readl(EXYNOS4_EPLL_CON1));
1505 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1506 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1507 __raw_readl(EXYNOS4_VPLL_CON1));
1512 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1513 clk_fout_mpll.rate = mpll;
1514 clk_fout_epll.rate = epll;
1515 clk_fout_vpll.ops = &exynos4_vpll_ops;
1516 clk_fout_vpll.rate = vpll;
1518 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1519 apll, mpll, epll, vpll);
1521 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1522 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1524 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1525 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1526 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1527 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1529 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1530 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1531 armclk, sclk_dmc, aclk_200,
1532 aclk_100, aclk_160, aclk_133);
1534 clk_f.rate = armclk;
1535 clk_h.rate = sclk_dmc;
1536 clk_p.rate = aclk_100;
1538 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1539 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1542 static struct clk *exynos4_clks[] __initdata = {
1543 &exynos4_clk_sclk_hdmi27m,
1544 &exynos4_clk_sclk_hdmiphy,
1545 &exynos4_clk_sclk_usbphy0,
1546 &exynos4_clk_sclk_usbphy1,
1549 #ifdef CONFIG_PM_SLEEP
1550 static int exynos4_clock_suspend(void)
1552 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1556 static void exynos4_clock_resume(void)
1558 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1562 #define exynos4_clock_suspend NULL
1563 #define exynos4_clock_resume NULL
1566 static struct syscore_ops exynos4_clock_syscore_ops = {
1567 .suspend = exynos4_clock_suspend,
1568 .resume = exynos4_clock_resume,
1571 void __init exynos4_register_clocks(void)
1575 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1577 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1578 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1580 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1581 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1583 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1584 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1586 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1587 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1589 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1590 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1591 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1593 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1594 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1595 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1597 register_syscore_ops(&exynos4_clock_syscore_ops);
1598 s3c24xx_register_clock(&dummy_apb_pclk);