2 * linux/arch/arm/mach-exynos4/clock-exynos4210.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * EXYNOS4210 - Clock support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/syscore_ops.h>
20 #include <plat/cpu-freq.h>
21 #include <plat/clock.h>
24 #include <plat/s5p-clock.h>
25 #include <plat/clock-clksrc.h>
26 #include <plat/exynos4.h>
29 #include <mach/hardware.h>
31 #include <mach/regs-clock.h>
32 #include <mach/exynos4-clock.h>
34 static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKDIV_LCD1),
39 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
40 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
41 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
42 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
45 static struct clksrc_clk *sysclks[] = {
46 /* nothing here yet */
49 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
51 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
54 static struct clksrc_clk clksrcs[] = {
59 .enable = exynos4_clksrc_mask_fsys_ctrl,
62 .sources = &clkset_mout_corebus,
63 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
64 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
68 .devname = "exynos4-fb.1",
69 .enable = exynos4_clksrc_mask_lcd1_ctrl,
72 .sources = &clkset_group,
73 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
74 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
78 static struct clk init_clocks_off[] = {
82 .parent = &clk_aclk_133.clk,
83 .enable = exynos4_clk_ip_fsys_ctrl,
88 .parent = &clk_aclk_133.clk,
89 .enable = exynos4_clk_ip_fsys_ctrl,
93 .devname = "exynos4-fb.1",
94 .enable = exynos4_clk_ip_lcd1_ctrl,
99 #ifdef CONFIG_PM_SLEEP
100 static int exynos4210_clock_suspend(void)
102 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
107 static void exynos4210_clock_resume(void)
109 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
113 #define exynos4210_clock_suspend NULL
114 #define exynos4210_clock_resume NULL
117 struct syscore_ops exynos4210_clock_syscore_ops = {
118 .suspend = exynos4210_clock_suspend,
119 .resume = exynos4210_clock_resume,
122 void __init exynos4210_register_clocks(void)
126 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
127 clk_mout_mpll.reg_src.shift = 8;
128 clk_mout_mpll.reg_src.size = 1;
130 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
131 s3c_register_clksrc(sysclks[ptr], 1);
133 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
135 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
136 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
138 register_syscore_ops(&exynos4210_clock_syscore_ops);