2 * linux/arch/arm/mach-exynos4/clock-exynos4212.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * EXYNOS4212 - Clock support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/syscore_ops.h>
20 #include <plat/cpu-freq.h>
21 #include <plat/clock.h>
24 #include <plat/s5p-clock.h>
25 #include <plat/clock-clksrc.h>
28 #include <mach/hardware.h>
30 #include <mach/regs-clock.h>
31 #include <mach/exynos4-clock.h>
35 static struct sleep_save exynos4212_clock_save[] = {
36 SAVE_ITEM(S5P_CLKSRC_IMAGE),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
39 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
42 static struct clk *clk_src_mpll_user_list[] = {
44 [1] = &clk_mout_mpll.clk,
47 static struct clksrc_sources clk_src_mpll_user = {
48 .sources = clk_src_mpll_user_list,
49 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
52 static struct clksrc_clk clk_mout_mpll_user = {
54 .name = "mout_mpll_user",
56 .sources = &clk_src_mpll_user,
57 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
60 static struct clksrc_clk *sysclks[] = {
64 static struct clksrc_clk clksrcs[] = {
65 /* nothing here yet */
68 static struct clk init_clocks_off[] = {
69 /* nothing here yet */
72 #ifdef CONFIG_PM_SLEEP
73 static int exynos4212_clock_suspend(void)
75 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
80 static void exynos4212_clock_resume(void)
82 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
86 #define exynos4212_clock_suspend NULL
87 #define exynos4212_clock_resume NULL
90 struct syscore_ops exynos4212_clock_syscore_ops = {
91 .suspend = exynos4212_clock_suspend,
92 .resume = exynos4212_clock_resume,
95 void __init exynos4212_register_clocks(void)
99 /* usbphy1 is removed */
100 clkset_group_list[4] = NULL;
102 /* mout_mpll_user is used */
103 clkset_group_list[6] = &clk_mout_mpll_user.clk;
104 clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
106 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
107 clk_mout_mpll.reg_src.shift = 12;
108 clk_mout_mpll.reg_src.size = 1;
110 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
111 s3c_register_clksrc(sysclks[ptr], 1);
113 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
115 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
116 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
118 register_syscore_ops(&exynos4212_clock_syscore_ops);