2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4212 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
26 #include <mach/hardware.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
32 #include "clock-exynos4.h"
34 #ifdef CONFIG_PM_SLEEP
35 static struct sleep_save exynos4212_clock_save[] = {
36 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
37 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
38 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
39 SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
43 static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
45 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
48 static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
50 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
53 static struct clk *clk_src_mpll_user_list[] = {
55 [1] = &exynos4_clk_mout_mpll.clk,
58 static struct clksrc_sources clk_src_mpll_user = {
59 .sources = clk_src_mpll_user_list,
60 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
63 static struct clksrc_clk clk_mout_mpll_user = {
65 .name = "mout_mpll_user",
67 .sources = &clk_src_mpll_user,
68 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
71 static struct clksrc_clk *sysclks[] = {
75 static struct clksrc_clk clksrcs[] = {
76 /* nothing here yet */
79 static struct clk init_clocks_off[] = {
81 .name = SYSMMU_CLOCK_NAME,
82 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
83 .enable = exynos4_clk_ip_dmc_ctrl,
86 .name = SYSMMU_CLOCK_NAME,
87 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
88 .enable = exynos4212_clk_ip_isp0_ctrl,
91 .name = SYSMMU_CLOCK_NAME2,
92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
93 .enable = exynos4212_clk_ip_isp1_ctrl,
97 .devname = "exynos-fimc-lite.0",
98 .enable = exynos4212_clk_ip_isp0_ctrl,
102 .devname = "exynos-fimc-lite.1",
103 .enable = exynos4212_clk_ip_isp0_ctrl,
108 #ifdef CONFIG_PM_SLEEP
109 static int exynos4212_clock_suspend(void)
111 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
116 static void exynos4212_clock_resume(void)
118 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
122 #define exynos4212_clock_suspend NULL
123 #define exynos4212_clock_resume NULL
126 static struct syscore_ops exynos4212_clock_syscore_ops = {
127 .suspend = exynos4212_clock_suspend,
128 .resume = exynos4212_clock_resume,
131 void __init exynos4212_register_clocks(void)
135 /* usbphy1 is removed */
136 exynos4_clkset_group_list[4] = NULL;
138 /* mout_mpll_user is used */
139 exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
140 exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
142 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
143 exynos4_clk_mout_mpll.reg_src.shift = 12;
144 exynos4_clk_mout_mpll.reg_src.size = 1;
146 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
147 s3c_register_clksrc(sysclks[ptr], 1);
149 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
151 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
152 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
154 register_syscore_ops(&exynos4212_clock_syscore_ops);