2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
21 #include <linux/of_irq.h>
23 #include <asm/proc-fns.h>
24 #include <asm/exception.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/hardware/gic.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29 #include <asm/cacheflush.h>
31 #include <mach/regs-irq.h>
32 #include <mach/regs-pmu.h>
33 #include <mach/regs-gpio.h>
37 #include <plat/clock.h>
38 #include <plat/devs.h>
40 #include <plat/sdhci.h>
41 #include <plat/gpio-cfg.h>
42 #include <plat/adc-core.h>
43 #include <plat/fb-core.h>
44 #include <plat/fimc-core.h>
45 #include <plat/iic-core.h>
46 #include <plat/tv-core.h>
47 #include <plat/regs-serial.h>
50 #define L2_AUX_VAL 0x7C470001
51 #define L2_AUX_MASK 0xC200ffff
53 static const char name_exynos4210[] = "EXYNOS4210";
54 static const char name_exynos4212[] = "EXYNOS4212";
55 static const char name_exynos4412[] = "EXYNOS4412";
56 static const char name_exynos5250[] = "EXYNOS5250";
58 static void exynos4_map_io(void);
59 static void exynos5_map_io(void);
60 static void exynos4_init_clocks(int xtal);
61 static void exynos5_init_clocks(int xtal);
62 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
63 static int exynos_init(void);
65 static struct cpu_table cpu_ids[] __initdata = {
67 .idcode = EXYNOS4210_CPU_ID,
68 .idmask = EXYNOS4_CPU_MASK,
69 .map_io = exynos4_map_io,
70 .init_clocks = exynos4_init_clocks,
71 .init_uarts = exynos_init_uarts,
73 .name = name_exynos4210,
75 .idcode = EXYNOS4212_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos_init_uarts,
81 .name = name_exynos4212,
83 .idcode = EXYNOS4412_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos_init_uarts,
89 .name = name_exynos4412,
91 .idcode = EXYNOS5250_SOC_ID,
92 .idmask = EXYNOS5_SOC_MASK,
93 .map_io = exynos5_map_io,
94 .init_clocks = exynos5_init_clocks,
95 .init_uarts = exynos_init_uarts,
97 .name = name_exynos5250,
101 /* Initial IO mappings */
103 static struct map_desc exynos_iodesc[] __initdata = {
105 .virtual = (unsigned long)S5P_VA_CHIPID,
106 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
112 static struct map_desc exynos4_iodesc[] __initdata = {
114 .virtual = (unsigned long)S3C_VA_SYS,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
119 .virtual = (unsigned long)S3C_VA_TIMER,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
124 .virtual = (unsigned long)S3C_VA_WATCHDOG,
125 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
129 .virtual = (unsigned long)S5P_VA_SROMC,
130 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
134 .virtual = (unsigned long)S5P_VA_SYSTIMER,
135 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
139 .virtual = (unsigned long)S5P_VA_PMU,
140 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
144 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
149 .virtual = (unsigned long)S5P_VA_GIC_CPU,
150 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
154 .virtual = (unsigned long)S5P_VA_GIC_DIST,
155 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
159 .virtual = (unsigned long)S3C_VA_UART,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
164 .virtual = (unsigned long)S5P_VA_CMU,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
169 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
170 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
174 .virtual = (unsigned long)S5P_VA_L2CC,
175 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
179 .virtual = (unsigned long)S5P_VA_DMC0,
180 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
184 .virtual = (unsigned long)S5P_VA_DMC1,
185 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
189 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
190 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
196 static struct map_desc exynos4_iodesc0[] __initdata = {
198 .virtual = (unsigned long)S5P_VA_SYSRAM,
199 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
205 static struct map_desc exynos4_iodesc1[] __initdata = {
207 .virtual = (unsigned long)S5P_VA_SYSRAM,
208 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
214 static struct map_desc exynos5_iodesc[] __initdata = {
216 .virtual = (unsigned long)S3C_VA_SYS,
217 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
221 .virtual = (unsigned long)S3C_VA_TIMER,
222 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
226 .virtual = (unsigned long)S3C_VA_WATCHDOG,
227 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
231 .virtual = (unsigned long)S5P_VA_SROMC,
232 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
236 .virtual = (unsigned long)S5P_VA_SYSTIMER,
237 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
241 .virtual = (unsigned long)S5P_VA_SYSRAM,
242 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
246 .virtual = (unsigned long)S5P_VA_CMU,
247 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
248 .length = 144 * SZ_1K,
251 .virtual = (unsigned long)S5P_VA_PMU,
252 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
256 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
257 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
261 .virtual = (unsigned long)S3C_VA_UART,
262 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
266 .virtual = (unsigned long)S5P_VA_GIC_CPU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
271 .virtual = (unsigned long)S5P_VA_GIC_DIST,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
278 void exynos4_restart(char mode, const char *cmd)
280 __raw_writel(0x1, S5P_SWRESET);
283 void exynos5_restart(char mode, const char *cmd)
285 __raw_writel(0x1, EXYNOS_SWRESET);
291 * register the standard cpu IO areas
294 void __init exynos_init_io(struct map_desc *mach_desc, int size)
296 /* initialize the io descriptors we need for initialization */
297 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
299 iotable_init(mach_desc, size);
301 /* detect cpu id and rev. */
302 s5p_init_cpu(S5P_VA_CHIPID);
304 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
307 static void __init exynos4_map_io(void)
309 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
311 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
312 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
314 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
316 /* initialize device information early */
317 exynos4_default_sdhci0();
318 exynos4_default_sdhci1();
319 exynos4_default_sdhci2();
320 exynos4_default_sdhci3();
322 s3c_adc_setname("samsung-adc-v3");
324 s3c_fimc_setname(0, "exynos4-fimc");
325 s3c_fimc_setname(1, "exynos4-fimc");
326 s3c_fimc_setname(2, "exynos4-fimc");
327 s3c_fimc_setname(3, "exynos4-fimc");
329 s3c_sdhci_setname(0, "exynos4-sdhci");
330 s3c_sdhci_setname(1, "exynos4-sdhci");
331 s3c_sdhci_setname(2, "exynos4-sdhci");
332 s3c_sdhci_setname(3, "exynos4-sdhci");
334 /* The I2C bus controllers are directly compatible with s3c2440 */
335 s3c_i2c0_setname("s3c2440-i2c");
336 s3c_i2c1_setname("s3c2440-i2c");
337 s3c_i2c2_setname("s3c2440-i2c");
339 s5p_fb_setname(0, "exynos4-fb");
340 s5p_hdmi_setname("exynos4-hdmi");
343 static void __init exynos5_map_io(void)
345 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
347 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
348 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
349 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
350 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
352 s3c_sdhci_setname(0, "exynos4-sdhci");
353 s3c_sdhci_setname(1, "exynos4-sdhci");
354 s3c_sdhci_setname(2, "exynos4-sdhci");
355 s3c_sdhci_setname(3, "exynos4-sdhci");
357 /* The I2C bus controllers are directly compatible with s3c2440 */
358 s3c_i2c0_setname("s3c2440-i2c");
359 s3c_i2c1_setname("s3c2440-i2c");
360 s3c_i2c2_setname("s3c2440-i2c");
363 static void __init exynos4_init_clocks(int xtal)
365 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
367 s3c24xx_register_baseclocks(xtal);
368 s5p_register_clocks(xtal);
370 if (soc_is_exynos4210())
371 exynos4210_register_clocks();
372 else if (soc_is_exynos4212() || soc_is_exynos4412())
373 exynos4212_register_clocks();
375 exynos4_register_clocks();
376 exynos4_setup_clocks();
379 static void __init exynos5_init_clocks(int xtal)
381 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
383 s3c24xx_register_baseclocks(xtal);
384 s5p_register_clocks(xtal);
386 exynos5_register_clocks();
387 exynos5_setup_clocks();
390 #define COMBINER_ENABLE_SET 0x0
391 #define COMBINER_ENABLE_CLEAR 0x4
392 #define COMBINER_INT_STATUS 0xC
394 static DEFINE_SPINLOCK(irq_controller_lock);
396 struct combiner_chip_data {
397 unsigned int irq_offset;
398 unsigned int irq_mask;
402 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
404 static inline void __iomem *combiner_base(struct irq_data *data)
406 struct combiner_chip_data *combiner_data =
407 irq_data_get_irq_chip_data(data);
409 return combiner_data->base;
412 static void combiner_mask_irq(struct irq_data *data)
414 u32 mask = 1 << (data->irq % 32);
416 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
419 static void combiner_unmask_irq(struct irq_data *data)
421 u32 mask = 1 << (data->irq % 32);
423 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
426 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
428 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
429 struct irq_chip *chip = irq_get_chip(irq);
430 unsigned int cascade_irq, combiner_irq;
431 unsigned long status;
433 chained_irq_enter(chip, desc);
435 spin_lock(&irq_controller_lock);
436 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
437 spin_unlock(&irq_controller_lock);
438 status &= chip_data->irq_mask;
443 combiner_irq = __ffs(status);
445 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
446 if (unlikely(cascade_irq >= NR_IRQS))
447 do_bad_IRQ(cascade_irq, desc);
449 generic_handle_irq(cascade_irq);
452 chained_irq_exit(chip, desc);
455 static struct irq_chip combiner_chip = {
457 .irq_mask = combiner_mask_irq,
458 .irq_unmask = combiner_unmask_irq,
461 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
465 if (soc_is_exynos5250())
466 max_nr = EXYNOS5_MAX_COMBINER_NR;
468 max_nr = EXYNOS4_MAX_COMBINER_NR;
470 if (combiner_nr >= max_nr)
472 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
474 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
477 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
478 unsigned int irq_start)
483 if (soc_is_exynos5250())
484 max_nr = EXYNOS5_MAX_COMBINER_NR;
486 max_nr = EXYNOS4_MAX_COMBINER_NR;
488 if (combiner_nr >= max_nr)
491 combiner_data[combiner_nr].base = base;
492 combiner_data[combiner_nr].irq_offset = irq_start;
493 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
495 /* Disable all interrupts */
497 __raw_writel(combiner_data[combiner_nr].irq_mask,
498 base + COMBINER_ENABLE_CLEAR);
500 /* Setup the Linux IRQ subsystem */
502 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
503 + MAX_IRQ_IN_COMBINER; i++) {
504 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
505 irq_set_chip_data(i, &combiner_data[combiner_nr]);
506 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
511 static const struct of_device_id exynos4_dt_irq_match[] = {
512 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
517 void __init exynos4_init_irq(void)
520 unsigned int gic_bank_offset;
522 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
524 if (!of_have_populated_dt())
525 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
528 of_irq_init(exynos4_dt_irq_match);
531 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
533 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
534 COMBINER_IRQ(irq, 0));
535 combiner_cascade_irq(irq, IRQ_SPI(irq));
539 * The parameters of s5p_init_irq() are for VIC init.
540 * Theses parameters should be NULL and 0 because EXYNOS4
541 * uses GIC instead of VIC.
543 s5p_init_irq(NULL, 0);
546 void __init exynos5_init_irq(void)
551 of_irq_init(exynos4_dt_irq_match);
554 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
555 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
556 COMBINER_IRQ(irq, 0));
557 combiner_cascade_irq(irq, IRQ_SPI(irq));
561 * The parameters of s5p_init_irq() are for VIC init.
562 * Theses parameters should be NULL and 0 because EXYNOS4
563 * uses GIC instead of VIC.
565 s5p_init_irq(NULL, 0);
568 struct bus_type exynos_subsys = {
569 .name = "exynos-core",
570 .dev_name = "exynos-core",
573 static struct device exynos4_dev = {
574 .bus = &exynos_subsys,
577 static int __init exynos_core_init(void)
579 return subsys_system_register(&exynos_subsys, NULL);
581 core_initcall(exynos_core_init);
583 #ifdef CONFIG_CACHE_L2X0
584 static int __init exynos4_l2x0_cache_init(void)
588 if (soc_is_exynos5250())
591 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
593 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
594 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
598 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
599 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
600 /* TAG, Data Latency Control: 2 cycles */
601 l2x0_saved_regs.tag_latency = 0x110;
603 if (soc_is_exynos4212() || soc_is_exynos4412())
604 l2x0_saved_regs.data_latency = 0x120;
606 l2x0_saved_regs.data_latency = 0x110;
608 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
609 l2x0_saved_regs.pwr_ctrl =
610 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
612 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
614 __raw_writel(l2x0_saved_regs.tag_latency,
615 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
616 __raw_writel(l2x0_saved_regs.data_latency,
617 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
619 /* L2X0 Prefetch Control */
620 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
621 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
623 /* L2X0 Power Control */
624 __raw_writel(l2x0_saved_regs.pwr_ctrl,
625 S5P_VA_L2CC + L2X0_POWER_CTRL);
627 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
628 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
631 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
634 early_initcall(exynos4_l2x0_cache_init);
637 static int __init exynos5_l2_cache_init(void)
641 if (!soc_is_exynos5250())
644 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
645 "bic %0, %0, #(1 << 2)\n" /* cache disable */
646 "mcr p15, 0, %0, c1, c0, 0\n"
647 "mrc p15, 1, %0, c9, c0, 2\n"
650 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
652 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
653 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
654 "orr %0, %0, #(1 << 2)\n" /* cache enable */
655 "mcr p15, 0, %0, c1, c0, 0\n"
660 early_initcall(exynos5_l2_cache_init);
662 static int __init exynos_init(void)
664 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
666 return device_register(&exynos4_dev);
669 /* uart registration process */
671 static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
673 struct s3c2410_uartcfg *tcfg = cfg;
676 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
677 tcfg->has_fracval = 1;
679 if (soc_is_exynos5250())
680 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
682 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
685 static void __iomem *exynos_eint_base;
687 static DEFINE_SPINLOCK(eint_lock);
689 static unsigned int eint0_15_data[16];
691 static inline int exynos4_irq_to_gpio(unsigned int irq)
693 if (irq < IRQ_EINT(0))
698 return EXYNOS4_GPX0(irq);
702 return EXYNOS4_GPX1(irq);
706 return EXYNOS4_GPX2(irq);
710 return EXYNOS4_GPX3(irq);
715 static inline int exynos5_irq_to_gpio(unsigned int irq)
717 if (irq < IRQ_EINT(0))
722 return EXYNOS5_GPX0(irq);
726 return EXYNOS5_GPX1(irq);
730 return EXYNOS5_GPX2(irq);
734 return EXYNOS5_GPX3(irq);
739 static unsigned int exynos4_eint0_15_src_int[16] = {
758 static unsigned int exynos5_eint0_15_src_int[16] = {
776 static inline void exynos_irq_eint_mask(struct irq_data *data)
780 spin_lock(&eint_lock);
781 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
782 mask |= EINT_OFFSET_BIT(data->irq);
783 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
784 spin_unlock(&eint_lock);
787 static void exynos_irq_eint_unmask(struct irq_data *data)
791 spin_lock(&eint_lock);
792 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
793 mask &= ~(EINT_OFFSET_BIT(data->irq));
794 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
795 spin_unlock(&eint_lock);
798 static inline void exynos_irq_eint_ack(struct irq_data *data)
800 __raw_writel(EINT_OFFSET_BIT(data->irq),
801 EINT_PEND(exynos_eint_base, data->irq));
804 static void exynos_irq_eint_maskack(struct irq_data *data)
806 exynos_irq_eint_mask(data);
807 exynos_irq_eint_ack(data);
810 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
812 int offs = EINT_OFFSET(data->irq);
818 case IRQ_TYPE_EDGE_RISING:
819 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
822 case IRQ_TYPE_EDGE_FALLING:
823 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
826 case IRQ_TYPE_EDGE_BOTH:
827 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
830 case IRQ_TYPE_LEVEL_LOW:
831 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
834 case IRQ_TYPE_LEVEL_HIGH:
835 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
839 printk(KERN_ERR "No such irq type %d", type);
843 shift = (offs & 0x7) * 4;
846 spin_lock(&eint_lock);
847 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
849 ctrl |= newvalue << shift;
850 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
851 spin_unlock(&eint_lock);
853 if (soc_is_exynos5250())
854 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
856 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
861 static struct irq_chip exynos_irq_eint = {
862 .name = "exynos-eint",
863 .irq_mask = exynos_irq_eint_mask,
864 .irq_unmask = exynos_irq_eint_unmask,
865 .irq_mask_ack = exynos_irq_eint_maskack,
866 .irq_ack = exynos_irq_eint_ack,
867 .irq_set_type = exynos_irq_eint_set_type,
869 .irq_set_wake = s3c_irqext_wake,
874 * exynos4_irq_demux_eint
876 * This function demuxes the IRQ from from EINTs 16 to 31.
877 * It is designed to be inlined into the specific handler
878 * s5p_irq_demux_eintX_Y.
880 * Each EINT pend/mask registers handle eight of them.
882 static inline void exynos_irq_demux_eint(unsigned int start)
886 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
887 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
893 irq = fls(status) - 1;
894 generic_handle_irq(irq + start);
895 status &= ~(1 << irq);
899 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
901 struct irq_chip *chip = irq_get_chip(irq);
902 chained_irq_enter(chip, desc);
903 exynos_irq_demux_eint(IRQ_EINT(16));
904 exynos_irq_demux_eint(IRQ_EINT(24));
905 chained_irq_exit(chip, desc);
908 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
910 u32 *irq_data = irq_get_handler_data(irq);
911 struct irq_chip *chip = irq_get_chip(irq);
913 chained_irq_enter(chip, desc);
914 chip->irq_mask(&desc->irq_data);
917 chip->irq_ack(&desc->irq_data);
919 generic_handle_irq(*irq_data);
921 chip->irq_unmask(&desc->irq_data);
922 chained_irq_exit(chip, desc);
925 static int __init exynos_init_irq_eint(void)
929 if (soc_is_exynos5250())
930 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
932 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
934 if (exynos_eint_base == NULL) {
935 pr_err("unable to ioremap for EINT base address\n");
939 for (irq = 0 ; irq <= 31 ; irq++) {
940 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
942 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
945 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
947 for (irq = 0 ; irq <= 15 ; irq++) {
948 eint0_15_data[irq] = IRQ_EINT(irq);
950 if (soc_is_exynos5250()) {
951 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
952 &eint0_15_data[irq]);
953 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
954 exynos_irq_eint0_15);
956 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
957 &eint0_15_data[irq]);
958 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
959 exynos_irq_eint0_15);
965 arch_initcall(exynos_init_irq_eint);