arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <asm/proc-fns.h>
  24 #include <asm/exception.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/hardware/gic.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/regs-irq.h>
  31 #include <mach/regs-pmu.h>
  32 #include <mach/regs-gpio.h>
  33
  34 #include <plat/cpu.h>
  35 #include <plat/clock.h>
  36 #include <plat/devs.h>
  37 #include <plat/pm.h>
  38 #include <plat/sdhci.h>
  39 #include <plat/gpio-cfg.h>
  40 #include <plat/adc-core.h>
  41 #include <plat/fb-core.h>
  42 #include <plat/fimc-core.h>
  43 #include <plat/iic-core.h>
  44 #include <plat/tv-core.h>
  45 #include <plat/regs-serial.h>
  46
  47 #include "common.h"
  48
  49 static const char name_exynos4210[] = "EXYNOS4210";
  50 static const char name_exynos4212[] = "EXYNOS4212";
  51 static const char name_exynos4412[] = "EXYNOS4412";
  52
  53 static struct cpu_table cpu_ids[] __initdata = {
  54         {
  55                 .idcode         = EXYNOS4210_CPU_ID,
  56                 .idmask         = EXYNOS4_CPU_MASK,
  57                 .map_io         = exynos4_map_io,
  58                 .init_clocks    = exynos4_init_clocks,
  59                 .init_uarts     = exynos4_init_uarts,
  60                 .init           = exynos_init,
  61                 .name           = name_exynos4210,
  62         }, {
  63                 .idcode         = EXYNOS4212_CPU_ID,
  64                 .idmask         = EXYNOS4_CPU_MASK,
  65                 .map_io         = exynos4_map_io,
  66                 .init_clocks    = exynos4_init_clocks,
  67                 .init_uarts     = exynos4_init_uarts,
  68                 .init           = exynos_init,
  69                 .name           = name_exynos4212,
  70         }, {
  71                 .idcode         = EXYNOS4412_CPU_ID,
  72                 .idmask         = EXYNOS4_CPU_MASK,
  73                 .map_io         = exynos4_map_io,
  74                 .init_clocks    = exynos4_init_clocks,
  75                 .init_uarts     = exynos4_init_uarts,
  76                 .init           = exynos_init,
  77                 .name           = name_exynos4412,
  78         },
  79 };
  80
  81 /* Initial IO mappings */
  82
  83 static struct map_desc exynos_iodesc[] __initdata = {
  84         {
  85                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  86                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
  87                 .length         = SZ_4K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S3C_VA_SYS,
  91                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  92                 .length         = SZ_64K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S3C_VA_TIMER,
  96                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
  97                 .length         = SZ_16K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 101                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S5P_VA_SROMC,
 106                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 111                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)S5P_VA_PMU,
 116                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 117                 .length         = SZ_64K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 121                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 126                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 127                 .length         = SZ_64K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 131                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 132                 .length         = SZ_64K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S3C_VA_UART,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 137                 .length         = SZ_512K,
 138                 .type           = MT_DEVICE,
 139         },
 140 };
 141
 142 static struct map_desc exynos4_iodesc[] __initdata = {
 143         {
 144                 .virtual        = (unsigned long)S5P_VA_CMU,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 146                 .length         = SZ_128K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 151                 .length         = SZ_8K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_L2CC,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 156                 .length         = SZ_4K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_DMC0,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 161                 .length         = SZ_4K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 166                 .length         = SZ_4K,
 167                 .type           = MT_DEVICE,
 168         },
 169 };
 170
 171 static struct map_desc exynos4_iodesc0[] __initdata = {
 172         {
 173                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 174                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 175                 .length         = SZ_4K,
 176                 .type           = MT_DEVICE,
 177         },
 178 };
 179
 180 static struct map_desc exynos4_iodesc1[] __initdata = {
 181         {
 182                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 184                 .length         = SZ_4K,
 185                 .type           = MT_DEVICE,
 186         },
 187 };
 188
 189 static void exynos_idle(void)
 190 {
 191         if (!need_resched())
 192                 cpu_do_idle();
 193
 194         local_irq_enable();
 195 }
 196
 197 void exynos4_restart(char mode, const char *cmd)
 198 {
 199         __raw_writel(0x1, S5P_SWRESET);
 200 }
 201
 202 /*
 203  * exynos_map_io
 204  *
 205  * register the standard cpu IO areas
 206  */
 207
 208 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 209 {
 210         /* initialize the io descriptors we need for initialization */
 211         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 212         if (mach_desc)
 213                 iotable_init(mach_desc, size);
 214
 215         /* detect cpu id and rev. */
 216         s5p_init_cpu(S5P_VA_CHIPID);
 217
 218         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 219 }
 220
 221 void __init exynos4_map_io(void)
 222 {
 223         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 224
 225         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 226                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 227         else
 228                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 229
 230         /* initialize device information early */
 231         exynos4_default_sdhci0();
 232         exynos4_default_sdhci1();
 233         exynos4_default_sdhci2();
 234         exynos4_default_sdhci3();
 235
 236         s3c_adc_setname("samsung-adc-v3");
 237
 238         s3c_fimc_setname(0, "exynos4-fimc");
 239         s3c_fimc_setname(1, "exynos4-fimc");
 240         s3c_fimc_setname(2, "exynos4-fimc");
 241         s3c_fimc_setname(3, "exynos4-fimc");
 242
 243         /* The I2C bus controllers are directly compatible with s3c2440 */
 244         s3c_i2c0_setname("s3c2440-i2c");
 245         s3c_i2c1_setname("s3c2440-i2c");
 246         s3c_i2c2_setname("s3c2440-i2c");
 247
 248         s5p_fb_setname(0, "exynos4-fb");
 249         s5p_hdmi_setname("exynos4-hdmi");
 250 }
 251
 252 void __init exynos4_init_clocks(int xtal)
 253 {
 254         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 255
 256         s3c24xx_register_baseclocks(xtal);
 257         s5p_register_clocks(xtal);
 258
 259         if (soc_is_exynos4210())
 260                 exynos4210_register_clocks();
 261         else if (soc_is_exynos4212() || soc_is_exynos4412())
 262                 exynos4212_register_clocks();
 263
 264         exynos4_register_clocks();
 265         exynos4_setup_clocks();
 266 }
 267
 268 #define COMBINER_ENABLE_SET     0x0
 269 #define COMBINER_ENABLE_CLEAR   0x4
 270 #define COMBINER_INT_STATUS     0xC
 271
 272 static DEFINE_SPINLOCK(irq_controller_lock);
 273
 274 struct combiner_chip_data {
 275         unsigned int irq_offset;
 276         unsigned int irq_mask;
 277         void __iomem *base;
 278 };
 279
 280 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 281
 282 static inline void __iomem *combiner_base(struct irq_data *data)
 283 {
 284         struct combiner_chip_data *combiner_data =
 285                 irq_data_get_irq_chip_data(data);
 286
 287         return combiner_data->base;
 288 }
 289
 290 static void combiner_mask_irq(struct irq_data *data)
 291 {
 292         u32 mask = 1 << (data->irq % 32);
 293
 294         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 295 }
 296
 297 static void combiner_unmask_irq(struct irq_data *data)
 298 {
 299         u32 mask = 1 << (data->irq % 32);
 300
 301         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 302 }
 303
 304 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 305 {
 306         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 307         struct irq_chip *chip = irq_get_chip(irq);
 308         unsigned int cascade_irq, combiner_irq;
 309         unsigned long status;
 310
 311         chained_irq_enter(chip, desc);
 312
 313         spin_lock(&irq_controller_lock);
 314         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 315         spin_unlock(&irq_controller_lock);
 316         status &= chip_data->irq_mask;
 317
 318         if (status == 0)
 319                 goto out;
 320
 321         combiner_irq = __ffs(status);
 322
 323         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 324         if (unlikely(cascade_irq >= NR_IRQS))
 325                 do_bad_IRQ(cascade_irq, desc);
 326         else
 327                 generic_handle_irq(cascade_irq);
 328
 329  out:
 330         chained_irq_exit(chip, desc);
 331 }
 332
 333 static struct irq_chip combiner_chip = {
 334         .name           = "COMBINER",
 335         .irq_mask       = combiner_mask_irq,
 336         .irq_unmask     = combiner_unmask_irq,
 337 };
 338
 339 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 340 {
 341         if (combiner_nr >= MAX_COMBINER_NR)
 342                 BUG();
 343         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 344                 BUG();
 345         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 346 }
 347
 348 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 349                           unsigned int irq_start)
 350 {
 351         unsigned int i;
 352
 353         if (combiner_nr >= MAX_COMBINER_NR)
 354                 BUG();
 355
 356         combiner_data[combiner_nr].base = base;
 357         combiner_data[combiner_nr].irq_offset = irq_start;
 358         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 359
 360         /* Disable all interrupts */
 361
 362         __raw_writel(combiner_data[combiner_nr].irq_mask,
 363                      base + COMBINER_ENABLE_CLEAR);
 364
 365         /* Setup the Linux IRQ subsystem */
 366
 367         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
 368                                 + MAX_IRQ_IN_COMBINER; i++) {
 369                 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
 370                 irq_set_chip_data(i, &combiner_data[combiner_nr]);
 371                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 372         }
 373 }
 374
 375 #ifdef CONFIG_OF
 376 static const struct of_device_id exynos4_dt_irq_match[] = {
 377         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 378         {},
 379 };
 380 #endif
 381
 382 void __init exynos4_init_irq(void)
 383 {
 384         int irq;
 385         unsigned int gic_bank_offset;
 386
 387         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 388
 389         if (!of_have_populated_dt())
 390                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
 391 #ifdef CONFIG_OF
 392         else
 393                 of_irq_init(exynos4_dt_irq_match);
 394 #endif
 395
 396         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 397
 398                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 399                                 COMBINER_IRQ(irq, 0));
 400                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 401         }
 402
 403         /*
 404          * The parameters of s5p_init_irq() are for VIC init.
 405          * Theses parameters should be NULL and 0 because EXYNOS4
 406          * uses GIC instead of VIC.
 407          */
 408         s5p_init_irq(NULL, 0);
 409 }
 410
 411 struct bus_type exynos4_subsys = {
 412         .name           = "exynos4-core",
 413         .dev_name       = "exynos4-core",
 414 };
 415
 416 static struct device exynos4_dev = {
 417         .bus    = &exynos4_subsys,
 418 };
 419
 420 static int __init exynos4_core_init(void)
 421 {
 422         return subsys_system_register(&exynos4_subsys, NULL);
 423 }
 424 core_initcall(exynos4_core_init);
 425
 426 #ifdef CONFIG_CACHE_L2X0
 427 static int __init exynos4_l2x0_cache_init(void)
 428 {
 429         /* TAG, Data Latency Control: 2cycle */
 430         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 431
 432         if (soc_is_exynos4210())
 433                 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 434         else if (soc_is_exynos4212() || soc_is_exynos4412())
 435                 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 436
 437         /* L2X0 Prefetch Control */
 438         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 439
 440         /* L2X0 Power Control */
 441         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 442                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 443
 444         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 445
 446         return 0;
 447 }
 448
 449 early_initcall(exynos4_l2x0_cache_init);
 450 #endif
 451
 452 int __init exynos_init(void)
 453 {
 454         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 455
 456         /* set idle function */
 457         pm_idle = exynos_idle;
 458
 459         return device_register(&exynos4_dev);
 460 }
 461
 462 /* uart registration process */
 463
 464 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 465 {
 466         struct s3c2410_uartcfg *tcfg = cfg;
 467         u32 ucnt;
 468
 469         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 470                 tcfg->has_fracval = 1;
 471
 472         s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
 473 }
 474
 475 static DEFINE_SPINLOCK(eint_lock);
 476
 477 static unsigned int eint0_15_data[16];
 478
 479 static unsigned int exynos4_get_irq_nr(unsigned int number)
 480 {
 481         u32 ret = 0;
 482
 483         switch (number) {
 484         case 0 ... 3:
 485                 ret = (number + IRQ_EINT0);
 486                 break;
 487         case 4 ... 7:
 488                 ret = (number + (IRQ_EINT4 - 4));
 489                 break;
 490         case 8 ... 15:
 491                 ret = (number + (IRQ_EINT8 - 8));
 492                 break;
 493         default:
 494                 printk(KERN_ERR "number available : %d\n", number);
 495         }
 496
 497         return ret;
 498 }
 499
 500 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 501 {
 502         u32 mask;
 503
 504         spin_lock(&eint_lock);
 505         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 506         mask |= eint_irq_to_bit(data->irq);
 507         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 508         spin_unlock(&eint_lock);
 509 }
 510
 511 static void exynos4_irq_eint_unmask(struct irq_data *data)
 512 {
 513         u32 mask;
 514
 515         spin_lock(&eint_lock);
 516         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 517         mask &= ~(eint_irq_to_bit(data->irq));
 518         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 519         spin_unlock(&eint_lock);
 520 }
 521
 522 static inline void exynos4_irq_eint_ack(struct irq_data *data)
 523 {
 524         __raw_writel(eint_irq_to_bit(data->irq),
 525                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 526 }
 527
 528 static void exynos4_irq_eint_maskack(struct irq_data *data)
 529 {
 530         exynos4_irq_eint_mask(data);
 531         exynos4_irq_eint_ack(data);
 532 }
 533
 534 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 535 {
 536         int offs = EINT_OFFSET(data->irq);
 537         int shift;
 538         u32 ctrl, mask;
 539         u32 newvalue = 0;
 540
 541         switch (type) {
 542         case IRQ_TYPE_EDGE_RISING:
 543                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 544                 break;
 545
 546         case IRQ_TYPE_EDGE_FALLING:
 547                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 548                 break;
 549
 550         case IRQ_TYPE_EDGE_BOTH:
 551                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 552                 break;
 553
 554         case IRQ_TYPE_LEVEL_LOW:
 555                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 556                 break;
 557
 558         case IRQ_TYPE_LEVEL_HIGH:
 559                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 560                 break;
 561
 562         default:
 563                 printk(KERN_ERR "No such irq type %d", type);
 564                 return -EINVAL;
 565         }
 566
 567         shift = (offs & 0x7) * 4;
 568         mask = 0x7 << shift;
 569
 570         spin_lock(&eint_lock);
 571         ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
 572         ctrl &= ~mask;
 573         ctrl |= newvalue << shift;
 574         __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
 575         spin_unlock(&eint_lock);
 576
 577         switch (offs) {
 578         case 0 ... 7:
 579                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
 580                 break;
 581         case 8 ... 15:
 582                 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
 583                 break;
 584         case 16 ... 23:
 585                 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
 586                 break;
 587         case 24 ... 31:
 588                 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
 589                 break;
 590         default:
 591                 printk(KERN_ERR "No such irq number %d", offs);
 592         }
 593
 594         return 0;
 595 }
 596
 597 static struct irq_chip exynos4_irq_eint = {
 598         .name           = "exynos4-eint",
 599         .irq_mask       = exynos4_irq_eint_mask,
 600         .irq_unmask     = exynos4_irq_eint_unmask,
 601         .irq_mask_ack   = exynos4_irq_eint_maskack,
 602         .irq_ack        = exynos4_irq_eint_ack,
 603         .irq_set_type   = exynos4_irq_eint_set_type,
 604 #ifdef CONFIG_PM
 605         .irq_set_wake   = s3c_irqext_wake,
 606 #endif
 607 };
 608
 609 /*
 610  * exynos4_irq_demux_eint
 611  *
 612  * This function demuxes the IRQ from from EINTs 16 to 31.
 613  * It is designed to be inlined into the specific handler
 614  * s5p_irq_demux_eintX_Y.
 615  *
 616  * Each EINT pend/mask registers handle eight of them.
 617  */
 618 static inline void exynos4_irq_demux_eint(unsigned int start)
 619 {
 620         unsigned int irq;
 621
 622         u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
 623         u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
 624
 625         status &= ~mask;
 626         status &= 0xff;
 627
 628         while (status) {
 629                 irq = fls(status) - 1;
 630                 generic_handle_irq(irq + start);
 631                 status &= ~(1 << irq);
 632         }
 633 }
 634
 635 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 636 {
 637         struct irq_chip *chip = irq_get_chip(irq);
 638         chained_irq_enter(chip, desc);
 639         exynos4_irq_demux_eint(IRQ_EINT(16));
 640         exynos4_irq_demux_eint(IRQ_EINT(24));
 641         chained_irq_exit(chip, desc);
 642 }
 643
 644 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 645 {
 646         u32 *irq_data = irq_get_handler_data(irq);
 647         struct irq_chip *chip = irq_get_chip(irq);
 648
 649         chained_irq_enter(chip, desc);
 650         chip->irq_mask(&desc->irq_data);
 651
 652         if (chip->irq_ack)
 653                 chip->irq_ack(&desc->irq_data);
 654
 655         generic_handle_irq(*irq_data);
 656
 657         chip->irq_unmask(&desc->irq_data);
 658         chained_irq_exit(chip, desc);
 659 }
 660
 661 int __init exynos4_init_irq_eint(void)
 662 {
 663         int irq;
 664
 665         for (irq = 0 ; irq <= 31 ; irq++) {
 666                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 667                                          handle_level_irq);
 668                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 669         }
 670
 671         irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 672
 673         for (irq = 0 ; irq <= 15 ; irq++) {
 674                 eint0_15_data[irq] = IRQ_EINT(irq);
 675
 676                 irq_set_handler_data(exynos4_get_irq_nr(irq),
 677                                      &eint0_15_data[irq]);
 678                 irq_set_chained_handler(exynos4_get_irq_nr(irq),
 679                                         exynos4_irq_eint0_15);
 680         }
 681
 682         return 0;
 683 }
 684 arch_initcall(exynos4_init_irq_eint);