2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for EXYNOS
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqchip.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/sched.h>
20 #include <linux/serial_core.h>
22 #include <linux/of_fdt.h>
23 #include <linux/of_irq.h>
24 #include <linux/export.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip.h>
27 #include <linux/of_address.h>
28 #include <linux/irqchip/arm-gic.h>
30 #include <asm/proc-fns.h>
31 #include <asm/exception.h>
32 #include <asm/hardware/cache-l2x0.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/irq.h>
35 #include <asm/cacheflush.h>
37 #include <mach/regs-irq.h>
38 #include <mach/regs-pmu.h>
39 #include <mach/regs-gpio.h>
42 #include <plat/clock.h>
43 #include <plat/devs.h>
45 #include <plat/sdhci.h>
46 #include <plat/gpio-cfg.h>
47 #include <plat/adc-core.h>
48 #include <plat/fb-core.h>
49 #include <plat/fimc-core.h>
50 #include <plat/iic-core.h>
51 #include <plat/tv-core.h>
52 #include <plat/spi-core.h>
53 #include <plat/regs-serial.h>
56 #define L2_AUX_VAL 0x7C470001
57 #define L2_AUX_MASK 0xC200ffff
59 static const char name_exynos4210[] = "EXYNOS4210";
60 static const char name_exynos4212[] = "EXYNOS4212";
61 static const char name_exynos4412[] = "EXYNOS4412";
62 static const char name_exynos5250[] = "EXYNOS5250";
63 static const char name_exynos5440[] = "EXYNOS5440";
65 static void exynos4_map_io(void);
66 static void exynos5_map_io(void);
67 static void exynos5440_map_io(void);
68 static void exynos4_init_clocks(int xtal);
69 static void exynos5_init_clocks(int xtal);
70 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
71 static int exynos_init(void);
73 static struct cpu_table cpu_ids[] __initdata = {
75 .idcode = EXYNOS4210_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts,
81 .name = name_exynos4210,
83 .idcode = EXYNOS4212_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
87 .init_uarts = exynos4_init_uarts,
89 .name = name_exynos4212,
91 .idcode = EXYNOS4412_CPU_ID,
92 .idmask = EXYNOS4_CPU_MASK,
93 .map_io = exynos4_map_io,
94 .init_clocks = exynos4_init_clocks,
95 .init_uarts = exynos4_init_uarts,
97 .name = name_exynos4412,
99 .idcode = EXYNOS5250_SOC_ID,
100 .idmask = EXYNOS5_SOC_MASK,
101 .map_io = exynos5_map_io,
102 .init_clocks = exynos5_init_clocks,
104 .name = name_exynos5250,
106 .idcode = EXYNOS5440_SOC_ID,
107 .idmask = EXYNOS5_SOC_MASK,
108 .map_io = exynos5440_map_io,
110 .name = name_exynos5440,
114 /* Initial IO mappings */
116 static struct map_desc exynos_iodesc[] __initdata = {
118 .virtual = (unsigned long)S5P_VA_CHIPID,
119 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
125 #ifdef CONFIG_ARCH_EXYNOS5
126 static struct map_desc exynos5440_iodesc[] __initdata = {
128 .virtual = (unsigned long)S5P_VA_CHIPID,
129 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
136 static struct map_desc exynos4_iodesc[] __initdata = {
138 .virtual = (unsigned long)S3C_VA_SYS,
139 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
143 .virtual = (unsigned long)S3C_VA_TIMER,
144 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
148 .virtual = (unsigned long)S3C_VA_WATCHDOG,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
153 .virtual = (unsigned long)S5P_VA_SROMC,
154 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
158 .virtual = (unsigned long)S5P_VA_SYSTIMER,
159 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
163 .virtual = (unsigned long)S5P_VA_PMU,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
168 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
173 .virtual = (unsigned long)S5P_VA_GIC_CPU,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
178 .virtual = (unsigned long)S5P_VA_GIC_DIST,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
183 .virtual = (unsigned long)S3C_VA_UART,
184 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
188 .virtual = (unsigned long)S5P_VA_CMU,
189 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
193 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
194 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
198 .virtual = (unsigned long)S5P_VA_L2CC,
199 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
203 .virtual = (unsigned long)S5P_VA_DMC0,
204 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
208 .virtual = (unsigned long)S5P_VA_DMC1,
209 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
213 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
214 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
220 static struct map_desc exynos4_iodesc0[] __initdata = {
222 .virtual = (unsigned long)S5P_VA_SYSRAM,
223 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
229 static struct map_desc exynos4_iodesc1[] __initdata = {
231 .virtual = (unsigned long)S5P_VA_SYSRAM,
232 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
238 static struct map_desc exynos5_iodesc[] __initdata = {
240 .virtual = (unsigned long)S3C_VA_SYS,
241 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
245 .virtual = (unsigned long)S3C_VA_TIMER,
246 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
250 .virtual = (unsigned long)S3C_VA_WATCHDOG,
251 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
255 .virtual = (unsigned long)S5P_VA_SROMC,
256 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
260 .virtual = (unsigned long)S5P_VA_SYSRAM,
261 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
265 .virtual = (unsigned long)S5P_VA_CMU,
266 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
267 .length = 144 * SZ_1K,
270 .virtual = (unsigned long)S5P_VA_PMU,
271 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
275 .virtual = (unsigned long)S3C_VA_UART,
276 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
282 static struct map_desc exynos5440_iodesc0[] __initdata = {
284 .virtual = (unsigned long)S3C_VA_UART,
285 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
291 void exynos4_restart(char mode, const char *cmd)
293 __raw_writel(0x1, S5P_SWRESET);
296 void exynos5_restart(char mode, const char *cmd)
298 struct device_node *np;
302 if (of_machine_is_compatible("samsung,exynos5250")) {
304 addr = EXYNOS_SWRESET;
305 } else if (of_machine_is_compatible("samsung,exynos5440")) {
306 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
307 addr = of_iomap(np, 0) + 0xcc;
308 val = (0xfff << 20) | (0x1 << 16);
310 pr_err("%s: cannot support non-DT\n", __func__);
314 __raw_writel(val, addr);
317 void __init exynos_init_late(void)
319 if (of_machine_is_compatible("samsung,exynos5440"))
320 /* to be supported later */
323 exynos_pm_late_initcall();
329 * register the standard cpu IO areas
332 void __init exynos_init_io(struct map_desc *mach_desc, int size)
334 struct map_desc *iodesc = exynos_iodesc;
335 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
336 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
337 unsigned long root = of_get_flat_dt_root();
339 /* initialize the io descriptors we need for initialization */
340 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
341 iodesc = exynos5440_iodesc;
342 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
346 iotable_init(iodesc, iodesc_sz);
349 iotable_init(mach_desc, size);
351 /* detect cpu id and rev. */
352 s5p_init_cpu(S5P_VA_CHIPID);
354 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
357 static void __init exynos4_map_io(void)
359 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
361 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
362 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
364 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
366 /* initialize device information early */
367 exynos4_default_sdhci0();
368 exynos4_default_sdhci1();
369 exynos4_default_sdhci2();
370 exynos4_default_sdhci3();
372 s3c_adc_setname("samsung-adc-v3");
374 s3c_fimc_setname(0, "exynos4-fimc");
375 s3c_fimc_setname(1, "exynos4-fimc");
376 s3c_fimc_setname(2, "exynos4-fimc");
377 s3c_fimc_setname(3, "exynos4-fimc");
379 s3c_sdhci_setname(0, "exynos4-sdhci");
380 s3c_sdhci_setname(1, "exynos4-sdhci");
381 s3c_sdhci_setname(2, "exynos4-sdhci");
382 s3c_sdhci_setname(3, "exynos4-sdhci");
384 /* The I2C bus controllers are directly compatible with s3c2440 */
385 s3c_i2c0_setname("s3c2440-i2c");
386 s3c_i2c1_setname("s3c2440-i2c");
387 s3c_i2c2_setname("s3c2440-i2c");
389 s5p_fb_setname(0, "exynos4-fb");
390 s5p_hdmi_setname("exynos4-hdmi");
392 s3c64xx_spi_setname("exynos4210-spi");
395 static void __init exynos5_map_io(void)
397 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
400 static void __init exynos4_init_clocks(int xtal)
402 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
404 s3c24xx_register_baseclocks(xtal);
405 s5p_register_clocks(xtal);
407 if (soc_is_exynos4210())
408 exynos4210_register_clocks();
409 else if (soc_is_exynos4212() || soc_is_exynos4412())
410 exynos4212_register_clocks();
412 exynos4_register_clocks();
413 exynos4_setup_clocks();
416 static void __init exynos5440_map_io(void)
418 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
421 static void __init exynos5_init_clocks(int xtal)
423 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
425 /* EXYNOS5440 can support only common clock framework */
427 if (soc_is_exynos5440())
430 #ifdef CONFIG_SOC_EXYNOS5250
431 s3c24xx_register_baseclocks(xtal);
432 s5p_register_clocks(xtal);
434 exynos5_register_clocks();
435 exynos5_setup_clocks();
439 void __init exynos4_init_irq(void)
441 unsigned int gic_bank_offset;
443 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
445 if (!of_have_populated_dt())
446 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
452 if (!of_have_populated_dt())
453 combiner_init(S5P_VA_COMBINER_BASE, NULL);
456 * The parameters of s5p_init_irq() are for VIC init.
457 * Theses parameters should be NULL and 0 because EXYNOS4
458 * uses GIC instead of VIC.
460 s5p_init_irq(NULL, 0);
463 void __init exynos5_init_irq(void)
469 * The parameters of s5p_init_irq() are for VIC init.
470 * Theses parameters should be NULL and 0 because EXYNOS4
471 * uses GIC instead of VIC.
473 if (!of_machine_is_compatible("samsung,exynos5440"))
474 s5p_init_irq(NULL, 0);
476 gic_arch_extn.irq_set_wake = s3c_irq_wake;
479 struct bus_type exynos_subsys = {
480 .name = "exynos-core",
481 .dev_name = "exynos-core",
484 static struct device exynos4_dev = {
485 .bus = &exynos_subsys,
488 static int __init exynos_core_init(void)
490 return subsys_system_register(&exynos_subsys, NULL);
492 core_initcall(exynos_core_init);
494 #ifdef CONFIG_CACHE_L2X0
495 static int __init exynos4_l2x0_cache_init(void)
499 if (soc_is_exynos5250() || soc_is_exynos5440())
502 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
504 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
505 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
509 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
510 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
511 /* TAG, Data Latency Control: 2 cycles */
512 l2x0_saved_regs.tag_latency = 0x110;
514 if (soc_is_exynos4212() || soc_is_exynos4412())
515 l2x0_saved_regs.data_latency = 0x120;
517 l2x0_saved_regs.data_latency = 0x110;
519 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
520 l2x0_saved_regs.pwr_ctrl =
521 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
523 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
525 __raw_writel(l2x0_saved_regs.tag_latency,
526 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
527 __raw_writel(l2x0_saved_regs.data_latency,
528 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
530 /* L2X0 Prefetch Control */
531 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
532 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
534 /* L2X0 Power Control */
535 __raw_writel(l2x0_saved_regs.pwr_ctrl,
536 S5P_VA_L2CC + L2X0_POWER_CTRL);
538 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
539 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
542 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
545 early_initcall(exynos4_l2x0_cache_init);
548 static int __init exynos_init(void)
550 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
552 return device_register(&exynos4_dev);
555 /* uart registration process */
557 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
559 struct s3c2410_uartcfg *tcfg = cfg;
562 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
563 tcfg->has_fracval = 1;
565 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
568 static void __iomem *exynos_eint_base;
570 static DEFINE_SPINLOCK(eint_lock);
572 static unsigned int eint0_15_data[16];
574 static inline int exynos4_irq_to_gpio(unsigned int irq)
576 if (irq < IRQ_EINT(0))
581 return EXYNOS4_GPX0(irq);
585 return EXYNOS4_GPX1(irq);
589 return EXYNOS4_GPX2(irq);
593 return EXYNOS4_GPX3(irq);
598 static inline int exynos5_irq_to_gpio(unsigned int irq)
600 if (irq < IRQ_EINT(0))
605 return EXYNOS5_GPX0(irq);
609 return EXYNOS5_GPX1(irq);
613 return EXYNOS5_GPX2(irq);
617 return EXYNOS5_GPX3(irq);
622 static unsigned int exynos4_eint0_15_src_int[16] = {
641 static unsigned int exynos5_eint0_15_src_int[16] = {
659 static inline void exynos_irq_eint_mask(struct irq_data *data)
663 spin_lock(&eint_lock);
664 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
665 mask |= EINT_OFFSET_BIT(data->irq);
666 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
667 spin_unlock(&eint_lock);
670 static void exynos_irq_eint_unmask(struct irq_data *data)
674 spin_lock(&eint_lock);
675 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
676 mask &= ~(EINT_OFFSET_BIT(data->irq));
677 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
678 spin_unlock(&eint_lock);
681 static inline void exynos_irq_eint_ack(struct irq_data *data)
683 __raw_writel(EINT_OFFSET_BIT(data->irq),
684 EINT_PEND(exynos_eint_base, data->irq));
687 static void exynos_irq_eint_maskack(struct irq_data *data)
689 exynos_irq_eint_mask(data);
690 exynos_irq_eint_ack(data);
693 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
695 int offs = EINT_OFFSET(data->irq);
701 case IRQ_TYPE_EDGE_RISING:
702 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
705 case IRQ_TYPE_EDGE_FALLING:
706 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
709 case IRQ_TYPE_EDGE_BOTH:
710 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
713 case IRQ_TYPE_LEVEL_LOW:
714 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
717 case IRQ_TYPE_LEVEL_HIGH:
718 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
722 printk(KERN_ERR "No such irq type %d", type);
726 shift = (offs & 0x7) * 4;
729 spin_lock(&eint_lock);
730 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
732 ctrl |= newvalue << shift;
733 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
734 spin_unlock(&eint_lock);
736 if (soc_is_exynos5250())
737 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
739 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
744 static struct irq_chip exynos_irq_eint = {
745 .name = "exynos-eint",
746 .irq_mask = exynos_irq_eint_mask,
747 .irq_unmask = exynos_irq_eint_unmask,
748 .irq_mask_ack = exynos_irq_eint_maskack,
749 .irq_ack = exynos_irq_eint_ack,
750 .irq_set_type = exynos_irq_eint_set_type,
752 .irq_set_wake = s3c_irqext_wake,
757 * exynos4_irq_demux_eint
759 * This function demuxes the IRQ from from EINTs 16 to 31.
760 * It is designed to be inlined into the specific handler
761 * s5p_irq_demux_eintX_Y.
763 * Each EINT pend/mask registers handle eight of them.
765 static inline void exynos_irq_demux_eint(unsigned int start)
769 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
770 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
776 irq = fls(status) - 1;
777 generic_handle_irq(irq + start);
778 status &= ~(1 << irq);
782 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
784 struct irq_chip *chip = irq_get_chip(irq);
785 chained_irq_enter(chip, desc);
786 exynos_irq_demux_eint(IRQ_EINT(16));
787 exynos_irq_demux_eint(IRQ_EINT(24));
788 chained_irq_exit(chip, desc);
791 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
793 u32 *irq_data = irq_get_handler_data(irq);
794 struct irq_chip *chip = irq_get_chip(irq);
796 chained_irq_enter(chip, desc);
797 generic_handle_irq(*irq_data);
798 chained_irq_exit(chip, desc);
801 static int __init exynos_init_irq_eint(void)
805 #ifdef CONFIG_PINCTRL_SAMSUNG
807 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
808 * functionality along with support for external gpio and wakeup
809 * interrupts. If the samsung pinctrl driver is enabled and includes
810 * the wakeup interrupt support, then the setting up external wakeup
811 * interrupts here can be skipped. This check here is temporary to
812 * allow exynos4 platforms that do not use Samsung pinctrl driver to
813 * co-exist with platforms that do. When all of the Samsung Exynos4
814 * platforms switch over to using the pinctrl driver, the wakeup
815 * interrupt support code here can be completely removed.
817 static const struct of_device_id exynos_pinctrl_ids[] = {
818 { .compatible = "samsung,exynos4210-pinctrl", },
819 { .compatible = "samsung,exynos4x12-pinctrl", },
820 { .compatible = "samsung,exynos5250-pinctrl", },
822 struct device_node *pctrl_np, *wkup_np;
823 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
825 for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
826 if (of_device_is_available(pctrl_np)) {
827 wkup_np = of_find_compatible_node(pctrl_np, NULL,
834 if (soc_is_exynos5440())
837 if (soc_is_exynos5250())
838 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
840 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
842 if (exynos_eint_base == NULL) {
843 pr_err("unable to ioremap for EINT base address\n");
847 for (irq = 0 ; irq <= 31 ; irq++) {
848 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
850 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
853 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
855 for (irq = 0 ; irq <= 15 ; irq++) {
856 eint0_15_data[irq] = IRQ_EINT(irq);
858 if (soc_is_exynos5250()) {
859 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
860 &eint0_15_data[irq]);
861 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
862 exynos_irq_eint0_15);
864 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
865 &eint0_15_data[irq]);
866 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
867 exynos_irq_eint0_15);
873 arch_initcall(exynos_init_irq_eint);