arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/export.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25
  26 #include <asm/proc-fns.h>
  27 #include <asm/exception.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include <asm/hardware/gic.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/cacheflush.h>
  33
  34 #include <mach/regs-irq.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/regs-gpio.h>
  37 #include <mach/pmu.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/sdhci.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/adc-core.h>
  46 #include <plat/fb-core.h>
  47 #include <plat/fimc-core.h>
  48 #include <plat/iic-core.h>
  49 #include <plat/tv-core.h>
  50 #include <plat/regs-serial.h>
  51
  52 #include "common.h"
  53 #define L2_AUX_VAL 0x7C470001
  54 #define L2_AUX_MASK 0xC200ffff
  55
  56 static const char name_exynos4210[] = "EXYNOS4210";
  57 static const char name_exynos4212[] = "EXYNOS4212";
  58 static const char name_exynos4412[] = "EXYNOS4412";
  59 static const char name_exynos5250[] = "EXYNOS5250";
  60
  61 static void exynos4_map_io(void);
  62 static void exynos5_map_io(void);
  63 static void exynos4_init_clocks(int xtal);
  64 static void exynos5_init_clocks(int xtal);
  65 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  66 static int exynos_init(void);
  67
  68 static struct cpu_table cpu_ids[] __initdata = {
  69         {
  70                 .idcode         = EXYNOS4210_CPU_ID,
  71                 .idmask         = EXYNOS4_CPU_MASK,
  72                 .map_io         = exynos4_map_io,
  73                 .init_clocks    = exynos4_init_clocks,
  74                 .init_uarts     = exynos_init_uarts,
  75                 .init           = exynos_init,
  76                 .name           = name_exynos4210,
  77         }, {
  78                 .idcode         = EXYNOS4212_CPU_ID,
  79                 .idmask         = EXYNOS4_CPU_MASK,
  80                 .map_io         = exynos4_map_io,
  81                 .init_clocks    = exynos4_init_clocks,
  82                 .init_uarts     = exynos_init_uarts,
  83                 .init           = exynos_init,
  84                 .name           = name_exynos4212,
  85         }, {
  86                 .idcode         = EXYNOS4412_CPU_ID,
  87                 .idmask         = EXYNOS4_CPU_MASK,
  88                 .map_io         = exynos4_map_io,
  89                 .init_clocks    = exynos4_init_clocks,
  90                 .init_uarts     = exynos_init_uarts,
  91                 .init           = exynos_init,
  92                 .name           = name_exynos4412,
  93         }, {
  94                 .idcode         = EXYNOS5250_SOC_ID,
  95                 .idmask         = EXYNOS5_SOC_MASK,
  96                 .map_io         = exynos5_map_io,
  97                 .init_clocks    = exynos5_init_clocks,
  98                 .init_uarts     = exynos_init_uarts,
  99                 .init           = exynos_init,
 100                 .name           = name_exynos5250,
 101         },
 102 };
 103
 104 /* Initial IO mappings */
 105
 106 static struct map_desc exynos_iodesc[] __initdata = {
 107         {
 108                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 109                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE,
 112         },
 113 };
 114
 115 static struct map_desc exynos4_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S3C_VA_SYS,
 118                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 119                 .length         = SZ_64K,
 120                 .type           = MT_DEVICE,
 121         }, {
 122                 .virtual        = (unsigned long)S3C_VA_TIMER,
 123                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 124                 .length         = SZ_16K,
 125                 .type           = MT_DEVICE,
 126         }, {
 127                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 128                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE,
 131         }, {
 132                 .virtual        = (unsigned long)S5P_VA_SROMC,
 133                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 139                 .length         = SZ_4K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S5P_VA_PMU,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 144                 .length         = SZ_64K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 154                 .length         = SZ_64K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 159                 .length         = SZ_64K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S3C_VA_UART,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 164                 .length         = SZ_512K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_CMU,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 169                 .length         = SZ_128K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 174                 .length         = SZ_8K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_L2CC,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 179                 .length         = SZ_4K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S5P_VA_DMC0,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 184                 .length         = SZ_64K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_DMC1,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 189                 .length         = SZ_64K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 194                 .length         = SZ_4K,
 195                 .type           = MT_DEVICE,
 196         },
 197 };
 198
 199 static struct map_desc exynos4_iodesc0[] __initdata = {
 200         {
 201                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 202                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 203                 .length         = SZ_4K,
 204                 .type           = MT_DEVICE,
 205         },
 206 };
 207
 208 static struct map_desc exynos4_iodesc1[] __initdata = {
 209         {
 210                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 211                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 212                 .length         = SZ_4K,
 213                 .type           = MT_DEVICE,
 214         },
 215 };
 216
 217 static struct map_desc exynos5_iodesc[] __initdata = {
 218         {
 219                 .virtual        = (unsigned long)S3C_VA_SYS,
 220                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 221                 .length         = SZ_64K,
 222                 .type           = MT_DEVICE,
 223         }, {
 224                 .virtual        = (unsigned long)S3C_VA_TIMER,
 225                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 226                 .length         = SZ_16K,
 227                 .type           = MT_DEVICE,
 228         }, {
 229                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 230                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         }, {
 234                 .virtual        = (unsigned long)S5P_VA_SROMC,
 235                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 236                 .length         = SZ_4K,
 237                 .type           = MT_DEVICE,
 238         }, {
 239                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 240                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 241                 .length         = SZ_4K,
 242                 .type           = MT_DEVICE,
 243         }, {
 244                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 245                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 246                 .length         = SZ_4K,
 247                 .type           = MT_DEVICE,
 248         }, {
 249                 .virtual        = (unsigned long)S5P_VA_CMU,
 250                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 251                 .length         = 144 * SZ_1K,
 252                 .type           = MT_DEVICE,
 253         }, {
 254                 .virtual        = (unsigned long)S5P_VA_PMU,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 256                 .length         = SZ_64K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
 261                 .length         = SZ_4K,
 262                 .type           = MT_DEVICE,
 263         }, {
 264                 .virtual        = (unsigned long)S3C_VA_UART,
 265                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 266                 .length         = SZ_512K,
 267                 .type           = MT_DEVICE,
 268         }, {
 269                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 270                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
 271                 .length         = SZ_8K,
 272                 .type           = MT_DEVICE,
 273         }, {
 274                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 275                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
 276                 .length         = SZ_4K,
 277                 .type           = MT_DEVICE,
 278         },
 279 };
 280
 281 void exynos4_restart(char mode, const char *cmd)
 282 {
 283         __raw_writel(0x1, S5P_SWRESET);
 284 }
 285
 286 void exynos5_restart(char mode, const char *cmd)
 287 {
 288         __raw_writel(0x1, EXYNOS_SWRESET);
 289 }
 290
 291 /*
 292  * exynos_map_io
 293  *
 294  * register the standard cpu IO areas
 295  */
 296
 297 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 298 {
 299         /* initialize the io descriptors we need for initialization */
 300         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 301         if (mach_desc)
 302                 iotable_init(mach_desc, size);
 303
 304         /* detect cpu id and rev. */
 305         s5p_init_cpu(S5P_VA_CHIPID);
 306
 307         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 308 }
 309
 310 static void __init exynos4_map_io(void)
 311 {
 312         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 313
 314         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 315                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 316         else
 317                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 318
 319         /* initialize device information early */
 320         exynos4_default_sdhci0();
 321         exynos4_default_sdhci1();
 322         exynos4_default_sdhci2();
 323         exynos4_default_sdhci3();
 324
 325         s3c_adc_setname("samsung-adc-v3");
 326
 327         s3c_fimc_setname(0, "exynos4-fimc");
 328         s3c_fimc_setname(1, "exynos4-fimc");
 329         s3c_fimc_setname(2, "exynos4-fimc");
 330         s3c_fimc_setname(3, "exynos4-fimc");
 331
 332         s3c_sdhci_setname(0, "exynos4-sdhci");
 333         s3c_sdhci_setname(1, "exynos4-sdhci");
 334         s3c_sdhci_setname(2, "exynos4-sdhci");
 335         s3c_sdhci_setname(3, "exynos4-sdhci");
 336
 337         /* The I2C bus controllers are directly compatible with s3c2440 */
 338         s3c_i2c0_setname("s3c2440-i2c");
 339         s3c_i2c1_setname("s3c2440-i2c");
 340         s3c_i2c2_setname("s3c2440-i2c");
 341
 342         s5p_fb_setname(0, "exynos4-fb");
 343         s5p_hdmi_setname("exynos4-hdmi");
 344 }
 345
 346 static void __init exynos5_map_io(void)
 347 {
 348         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 349
 350         s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
 351         s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
 352         s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
 353         s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 354
 355         s3c_sdhci_setname(0, "exynos4-sdhci");
 356         s3c_sdhci_setname(1, "exynos4-sdhci");
 357         s3c_sdhci_setname(2, "exynos4-sdhci");
 358         s3c_sdhci_setname(3, "exynos4-sdhci");
 359
 360         /* The I2C bus controllers are directly compatible with s3c2440 */
 361         s3c_i2c0_setname("s3c2440-i2c");
 362         s3c_i2c1_setname("s3c2440-i2c");
 363         s3c_i2c2_setname("s3c2440-i2c");
 364 }
 365
 366 static void __init exynos4_init_clocks(int xtal)
 367 {
 368         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 369
 370         s3c24xx_register_baseclocks(xtal);
 371         s5p_register_clocks(xtal);
 372
 373         if (soc_is_exynos4210())
 374                 exynos4210_register_clocks();
 375         else if (soc_is_exynos4212() || soc_is_exynos4412())
 376                 exynos4212_register_clocks();
 377
 378         exynos4_register_clocks();
 379         exynos4_setup_clocks();
 380 }
 381
 382 static void __init exynos5_init_clocks(int xtal)
 383 {
 384         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 385
 386         s3c24xx_register_baseclocks(xtal);
 387         s5p_register_clocks(xtal);
 388
 389         exynos5_register_clocks();
 390         exynos5_setup_clocks();
 391 }
 392
 393 #define COMBINER_ENABLE_SET     0x0
 394 #define COMBINER_ENABLE_CLEAR   0x4
 395 #define COMBINER_INT_STATUS     0xC
 396
 397 static DEFINE_SPINLOCK(irq_controller_lock);
 398
 399 struct combiner_chip_data {
 400         unsigned int irq_offset;
 401         unsigned int irq_mask;
 402         void __iomem *base;
 403 };
 404
 405 static struct irq_domain *combiner_irq_domain;
 406 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 407
 408 static inline void __iomem *combiner_base(struct irq_data *data)
 409 {
 410         struct combiner_chip_data *combiner_data =
 411                 irq_data_get_irq_chip_data(data);
 412
 413         return combiner_data->base;
 414 }
 415
 416 static void combiner_mask_irq(struct irq_data *data)
 417 {
 418         u32 mask = 1 << (data->hwirq % 32);
 419
 420         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 421 }
 422
 423 static void combiner_unmask_irq(struct irq_data *data)
 424 {
 425         u32 mask = 1 << (data->hwirq % 32);
 426
 427         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 428 }
 429
 430 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 431 {
 432         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 433         struct irq_chip *chip = irq_get_chip(irq);
 434         unsigned int cascade_irq, combiner_irq;
 435         unsigned long status;
 436
 437         chained_irq_enter(chip, desc);
 438
 439         spin_lock(&irq_controller_lock);
 440         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 441         spin_unlock(&irq_controller_lock);
 442         status &= chip_data->irq_mask;
 443
 444         if (status == 0)
 445                 goto out;
 446
 447         combiner_irq = __ffs(status);
 448
 449         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 450         if (unlikely(cascade_irq >= NR_IRQS))
 451                 do_bad_IRQ(cascade_irq, desc);
 452         else
 453                 generic_handle_irq(cascade_irq);
 454
 455  out:
 456         chained_irq_exit(chip, desc);
 457 }
 458
 459 static struct irq_chip combiner_chip = {
 460         .name           = "COMBINER",
 461         .irq_mask       = combiner_mask_irq,
 462         .irq_unmask     = combiner_unmask_irq,
 463 };
 464
 465 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 466 {
 467         unsigned int max_nr;
 468
 469         if (soc_is_exynos5250())
 470                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 471         else
 472                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 473
 474         if (combiner_nr >= max_nr)
 475                 BUG();
 476         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 477                 BUG();
 478         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 479 }
 480
 481 static void __init combiner_init_one(unsigned int combiner_nr,
 482                                      void __iomem *base)
 483 {
 484         combiner_data[combiner_nr].base = base;
 485         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 486                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 487         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 488
 489         /* Disable all interrupts */
 490         __raw_writel(combiner_data[combiner_nr].irq_mask,
 491                      base + COMBINER_ENABLE_CLEAR);
 492 }
 493
 494 #ifdef CONFIG_OF
 495 static int combiner_irq_domain_xlate(struct irq_domain *d,
 496                                      struct device_node *controller,
 497                                      const u32 *intspec, unsigned int intsize,
 498                                      unsigned long *out_hwirq,
 499                                      unsigned int *out_type)
 500 {
 501         if (d->of_node != controller)
 502                 return -EINVAL;
 503
 504         if (intsize < 2)
 505                 return -EINVAL;
 506
 507         *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
 508         *out_type = 0;
 509
 510         return 0;
 511 }
 512 #else
 513 static int combiner_irq_domain_xlate(struct irq_domain *d,
 514                                      struct device_node *controller,
 515                                      const u32 *intspec, unsigned int intsize,
 516                                      unsigned long *out_hwirq,
 517                                      unsigned int *out_type)
 518 {
 519         return -EINVAL;
 520 }
 521 #endif
 522
 523 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 524                                    irq_hw_number_t hw)
 525 {
 526         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
 527         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
 528         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 529
 530         return 0;
 531 }
 532
 533 static struct irq_domain_ops combiner_irq_domain_ops = {
 534         .xlate  = combiner_irq_domain_xlate,
 535         .map    = combiner_irq_domain_map,
 536 };
 537
 538 void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
 539 {
 540         int i, irq, irq_base;
 541         unsigned int max_nr, nr_irq;
 542
 543         if (np) {
 544                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 545                         pr_warning("%s: number of combiners not specified, "
 546                                 "setting default as %d.\n",
 547                                 __func__, EXYNOS4_MAX_COMBINER_NR);
 548                         max_nr = EXYNOS4_MAX_COMBINER_NR;
 549                 }
 550         } else {
 551                 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 552                                                 EXYNOS4_MAX_COMBINER_NR;
 553         }
 554         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 555
 556         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
 557         if (IS_ERR_VALUE(irq_base)) {
 558                 irq_base = COMBINER_IRQ(0, 0);
 559                 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
 560         }
 561
 562         combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
 563                                 &combiner_irq_domain_ops, &combiner_data);
 564         if (WARN_ON(!combiner_irq_domain)) {
 565                 pr_warning("%s: irq domain init failed\n", __func__);
 566                 return;
 567         }
 568
 569         for (i = 0; i < max_nr; i++) {
 570                 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 571                 irq = IRQ_SPI(i);
 572 #ifdef CONFIG_OF
 573                 if (np)
 574                         irq = irq_of_parse_and_map(np, i);
 575 #endif
 576                 combiner_cascade_irq(i, irq);
 577         }
 578 }
 579
 580 #ifdef CONFIG_OF
 581 int __init combiner_of_init(struct device_node *np, struct device_node *parent)
 582 {
 583         void __iomem *combiner_base;
 584
 585         combiner_base = of_iomap(np, 0);
 586         if (!combiner_base) {
 587                 pr_err("%s: failed to map combiner registers\n", __func__);
 588                 return -ENXIO;
 589         }
 590
 591         combiner_init(combiner_base, np);
 592
 593         return 0;
 594 }
 595
 596 static const struct of_device_id exynos4_dt_irq_match[] = {
 597         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 598         { .compatible = "samsung,exynos4210-combiner",
 599                         .data = combiner_of_init, },
 600         {},
 601 };
 602 #endif
 603
 604 void __init exynos4_init_irq(void)
 605 {
 606         unsigned int gic_bank_offset;
 607
 608         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 609
 610         if (!of_have_populated_dt())
 611                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 612 #ifdef CONFIG_OF
 613         else
 614                 of_irq_init(exynos4_dt_irq_match);
 615 #endif
 616
 617         if (!of_have_populated_dt())
 618                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 619
 620         /*
 621          * The parameters of s5p_init_irq() are for VIC init.
 622          * Theses parameters should be NULL and 0 because EXYNOS4
 623          * uses GIC instead of VIC.
 624          */
 625         s5p_init_irq(NULL, 0);
 626 }
 627
 628 void __init exynos5_init_irq(void)
 629 {
 630 #ifdef CONFIG_OF
 631         of_irq_init(exynos4_dt_irq_match);
 632 #endif
 633         /*
 634          * The parameters of s5p_init_irq() are for VIC init.
 635          * Theses parameters should be NULL and 0 because EXYNOS4
 636          * uses GIC instead of VIC.
 637          */
 638         s5p_init_irq(NULL, 0);
 639 }
 640
 641 struct bus_type exynos_subsys = {
 642         .name           = "exynos-core",
 643         .dev_name       = "exynos-core",
 644 };
 645
 646 static struct device exynos4_dev = {
 647         .bus    = &exynos_subsys,
 648 };
 649
 650 static int __init exynos_core_init(void)
 651 {
 652         return subsys_system_register(&exynos_subsys, NULL);
 653 }
 654 core_initcall(exynos_core_init);
 655
 656 #ifdef CONFIG_CACHE_L2X0
 657 static int __init exynos4_l2x0_cache_init(void)
 658 {
 659         int ret;
 660
 661         if (soc_is_exynos5250())
 662                 return 0;
 663
 664         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 665         if (!ret) {
 666                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 667                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 668                 return 0;
 669         }
 670
 671         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 672                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 673                 /* TAG, Data Latency Control: 2 cycles */
 674                 l2x0_saved_regs.tag_latency = 0x110;
 675
 676                 if (soc_is_exynos4212() || soc_is_exynos4412())
 677                         l2x0_saved_regs.data_latency = 0x120;
 678                 else
 679                         l2x0_saved_regs.data_latency = 0x110;
 680
 681                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 682                 l2x0_saved_regs.pwr_ctrl =
 683                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 684
 685                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 686
 687                 __raw_writel(l2x0_saved_regs.tag_latency,
 688                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 689                 __raw_writel(l2x0_saved_regs.data_latency,
 690                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 691
 692                 /* L2X0 Prefetch Control */
 693                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 694                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 695
 696                 /* L2X0 Power Control */
 697                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 698                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 699
 700                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 701                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 702         }
 703
 704         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 705         return 0;
 706 }
 707 early_initcall(exynos4_l2x0_cache_init);
 708 #endif
 709
 710 static int __init exynos5_l2_cache_init(void)
 711 {
 712         unsigned int val;
 713
 714         if (!soc_is_exynos5250())
 715                 return 0;
 716
 717         asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
 718                      "bic %0, %0, #(1 << 2)\n"  /* cache disable */
 719                      "mcr p15, 0, %0, c1, c0, 0\n"
 720                      "mrc p15, 1, %0, c9, c0, 2\n"
 721                      : "=r"(val));
 722
 723         val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
 724
 725         asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
 726         asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
 727                      "orr %0, %0, #(1 << 2)\n"  /* cache enable */
 728                      "mcr p15, 0, %0, c1, c0, 0\n"
 729                      : : "r"(val));
 730
 731         return 0;
 732 }
 733 early_initcall(exynos5_l2_cache_init);
 734
 735 static int __init exynos_init(void)
 736 {
 737         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 738
 739         return device_register(&exynos4_dev);
 740 }
 741
 742 /* uart registration process */
 743
 744 static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 745 {
 746         struct s3c2410_uartcfg *tcfg = cfg;
 747         u32 ucnt;
 748
 749         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 750                 tcfg->has_fracval = 1;
 751
 752         if (soc_is_exynos5250())
 753                 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
 754         else
 755                 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 756 }
 757
 758 static void __iomem *exynos_eint_base;
 759
 760 static DEFINE_SPINLOCK(eint_lock);
 761
 762 static unsigned int eint0_15_data[16];
 763
 764 static inline int exynos4_irq_to_gpio(unsigned int irq)
 765 {
 766         if (irq < IRQ_EINT(0))
 767                 return -EINVAL;
 768
 769         irq -= IRQ_EINT(0);
 770         if (irq < 8)
 771                 return EXYNOS4_GPX0(irq);
 772
 773         irq -= 8;
 774         if (irq < 8)
 775                 return EXYNOS4_GPX1(irq);
 776
 777         irq -= 8;
 778         if (irq < 8)
 779                 return EXYNOS4_GPX2(irq);
 780
 781         irq -= 8;
 782         if (irq < 8)
 783                 return EXYNOS4_GPX3(irq);
 784
 785         return -EINVAL;
 786 }
 787
 788 static inline int exynos5_irq_to_gpio(unsigned int irq)
 789 {
 790         if (irq < IRQ_EINT(0))
 791                 return -EINVAL;
 792
 793         irq -= IRQ_EINT(0);
 794         if (irq < 8)
 795                 return EXYNOS5_GPX0(irq);
 796
 797         irq -= 8;
 798         if (irq < 8)
 799                 return EXYNOS5_GPX1(irq);
 800
 801         irq -= 8;
 802         if (irq < 8)
 803                 return EXYNOS5_GPX2(irq);
 804
 805         irq -= 8;
 806         if (irq < 8)
 807                 return EXYNOS5_GPX3(irq);
 808
 809         return -EINVAL;
 810 }
 811
 812 static unsigned int exynos4_eint0_15_src_int[16] = {
 813         EXYNOS4_IRQ_EINT0,
 814         EXYNOS4_IRQ_EINT1,
 815         EXYNOS4_IRQ_EINT2,
 816         EXYNOS4_IRQ_EINT3,
 817         EXYNOS4_IRQ_EINT4,
 818         EXYNOS4_IRQ_EINT5,
 819         EXYNOS4_IRQ_EINT6,
 820         EXYNOS4_IRQ_EINT7,
 821         EXYNOS4_IRQ_EINT8,
 822         EXYNOS4_IRQ_EINT9,
 823         EXYNOS4_IRQ_EINT10,
 824         EXYNOS4_IRQ_EINT11,
 825         EXYNOS4_IRQ_EINT12,
 826         EXYNOS4_IRQ_EINT13,
 827         EXYNOS4_IRQ_EINT14,
 828         EXYNOS4_IRQ_EINT15,
 829 };
 830
 831 static unsigned int exynos5_eint0_15_src_int[16] = {
 832         EXYNOS5_IRQ_EINT0,
 833         EXYNOS5_IRQ_EINT1,
 834         EXYNOS5_IRQ_EINT2,
 835         EXYNOS5_IRQ_EINT3,
 836         EXYNOS5_IRQ_EINT4,
 837         EXYNOS5_IRQ_EINT5,
 838         EXYNOS5_IRQ_EINT6,
 839         EXYNOS5_IRQ_EINT7,
 840         EXYNOS5_IRQ_EINT8,
 841         EXYNOS5_IRQ_EINT9,
 842         EXYNOS5_IRQ_EINT10,
 843         EXYNOS5_IRQ_EINT11,
 844         EXYNOS5_IRQ_EINT12,
 845         EXYNOS5_IRQ_EINT13,
 846         EXYNOS5_IRQ_EINT14,
 847         EXYNOS5_IRQ_EINT15,
 848 };
 849 static inline void exynos_irq_eint_mask(struct irq_data *data)
 850 {
 851         u32 mask;
 852
 853         spin_lock(&eint_lock);
 854         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 855         mask |= EINT_OFFSET_BIT(data->irq);
 856         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 857         spin_unlock(&eint_lock);
 858 }
 859
 860 static void exynos_irq_eint_unmask(struct irq_data *data)
 861 {
 862         u32 mask;
 863
 864         spin_lock(&eint_lock);
 865         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 866         mask &= ~(EINT_OFFSET_BIT(data->irq));
 867         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 868         spin_unlock(&eint_lock);
 869 }
 870
 871 static inline void exynos_irq_eint_ack(struct irq_data *data)
 872 {
 873         __raw_writel(EINT_OFFSET_BIT(data->irq),
 874                      EINT_PEND(exynos_eint_base, data->irq));
 875 }
 876
 877 static void exynos_irq_eint_maskack(struct irq_data *data)
 878 {
 879         exynos_irq_eint_mask(data);
 880         exynos_irq_eint_ack(data);
 881 }
 882
 883 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 884 {
 885         int offs = EINT_OFFSET(data->irq);
 886         int shift;
 887         u32 ctrl, mask;
 888         u32 newvalue = 0;
 889
 890         switch (type) {
 891         case IRQ_TYPE_EDGE_RISING:
 892                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 893                 break;
 894
 895         case IRQ_TYPE_EDGE_FALLING:
 896                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 897                 break;
 898
 899         case IRQ_TYPE_EDGE_BOTH:
 900                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 901                 break;
 902
 903         case IRQ_TYPE_LEVEL_LOW:
 904                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 905                 break;
 906
 907         case IRQ_TYPE_LEVEL_HIGH:
 908                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 909                 break;
 910
 911         default:
 912                 printk(KERN_ERR "No such irq type %d", type);
 913                 return -EINVAL;
 914         }
 915
 916         shift = (offs & 0x7) * 4;
 917         mask = 0x7 << shift;
 918
 919         spin_lock(&eint_lock);
 920         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 921         ctrl &= ~mask;
 922         ctrl |= newvalue << shift;
 923         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 924         spin_unlock(&eint_lock);
 925
 926         if (soc_is_exynos5250())
 927                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 928         else
 929                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 930
 931         return 0;
 932 }
 933
 934 static struct irq_chip exynos_irq_eint = {
 935         .name           = "exynos-eint",
 936         .irq_mask       = exynos_irq_eint_mask,
 937         .irq_unmask     = exynos_irq_eint_unmask,
 938         .irq_mask_ack   = exynos_irq_eint_maskack,
 939         .irq_ack        = exynos_irq_eint_ack,
 940         .irq_set_type   = exynos_irq_eint_set_type,
 941 #ifdef CONFIG_PM
 942         .irq_set_wake   = s3c_irqext_wake,
 943 #endif
 944 };
 945
 946 /*
 947  * exynos4_irq_demux_eint
 948  *
 949  * This function demuxes the IRQ from from EINTs 16 to 31.
 950  * It is designed to be inlined into the specific handler
 951  * s5p_irq_demux_eintX_Y.
 952  *
 953  * Each EINT pend/mask registers handle eight of them.
 954  */
 955 static inline void exynos_irq_demux_eint(unsigned int start)
 956 {
 957         unsigned int irq;
 958
 959         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 960         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 961
 962         status &= ~mask;
 963         status &= 0xff;
 964
 965         while (status) {
 966                 irq = fls(status) - 1;
 967                 generic_handle_irq(irq + start);
 968                 status &= ~(1 << irq);
 969         }
 970 }
 971
 972 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 973 {
 974         struct irq_chip *chip = irq_get_chip(irq);
 975         chained_irq_enter(chip, desc);
 976         exynos_irq_demux_eint(IRQ_EINT(16));
 977         exynos_irq_demux_eint(IRQ_EINT(24));
 978         chained_irq_exit(chip, desc);
 979 }
 980
 981 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 982 {
 983         u32 *irq_data = irq_get_handler_data(irq);
 984         struct irq_chip *chip = irq_get_chip(irq);
 985
 986         chained_irq_enter(chip, desc);
 987         chip->irq_mask(&desc->irq_data);
 988
 989         if (chip->irq_ack)
 990                 chip->irq_ack(&desc->irq_data);
 991
 992         generic_handle_irq(*irq_data);
 993
 994         chip->irq_unmask(&desc->irq_data);
 995         chained_irq_exit(chip, desc);
 996 }
 997
 998 static int __init exynos_init_irq_eint(void)
 999 {
1000         int irq;
1001
1002         if (soc_is_exynos5250())
1003                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1004         else
1005                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1006
1007         if (exynos_eint_base == NULL) {
1008                 pr_err("unable to ioremap for EINT base address\n");
1009                 return -ENOMEM;
1010         }
1011
1012         for (irq = 0 ; irq <= 31 ; irq++) {
1013                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
1014                                          handle_level_irq);
1015                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1016         }
1017
1018         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
1019
1020         for (irq = 0 ; irq <= 15 ; irq++) {
1021                 eint0_15_data[irq] = IRQ_EINT(irq);
1022
1023                 if (soc_is_exynos5250()) {
1024                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1025                                              &eint0_15_data[irq]);
1026                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1027                                                 exynos_irq_eint0_15);
1028                 } else {
1029                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1030                                              &eint0_15_data[irq]);
1031                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1032                                                 exynos_irq_eint0_15);
1033                 }
1034         }
1035
1036         return 0;
1037 }
1038 arch_initcall(exynos_init_irq_eint);