2 * SAMSUNG EXYNOS Flattened Device Tree enabled machine
4 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/serial_s3c.h>
17 #include <linux/of_address.h>
18 #include <linux/of_fdt.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/irqchip.h>
24 #include <asm/cacheflush.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28 #include <asm/memory.h>
35 void __iomem *pmu_base_addr;
37 static struct map_desc exynos4_iodesc[] __initdata = {
39 .virtual = (unsigned long)S3C_VA_SYS,
40 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
44 .virtual = (unsigned long)S3C_VA_TIMER,
45 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
49 .virtual = (unsigned long)S3C_VA_WATCHDOG,
50 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
54 .virtual = (unsigned long)S5P_VA_SROMC,
55 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
59 .virtual = (unsigned long)S5P_VA_SYSTIMER,
60 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
64 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
65 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
69 .virtual = (unsigned long)S5P_VA_GIC_CPU,
70 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
74 .virtual = (unsigned long)S5P_VA_GIC_DIST,
75 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
79 .virtual = (unsigned long)S5P_VA_CMU,
80 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
84 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
85 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
89 .virtual = (unsigned long)S5P_VA_L2CC,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
94 .virtual = (unsigned long)S5P_VA_DMC0,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
99 .virtual = (unsigned long)S5P_VA_DMC1,
100 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
104 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
105 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
111 static struct map_desc exynos5_iodesc[] __initdata = {
113 .virtual = (unsigned long)S3C_VA_SYS,
114 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
118 .virtual = (unsigned long)S3C_VA_TIMER,
119 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
123 .virtual = (unsigned long)S3C_VA_WATCHDOG,
124 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
128 .virtual = (unsigned long)S5P_VA_SROMC,
129 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
133 .virtual = (unsigned long)S5P_VA_CMU,
134 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
135 .length = 144 * SZ_1K,
140 static void exynos_restart(enum reboot_mode mode, const char *cmd)
142 struct device_node *np;
144 void __iomem *addr = pmu_base_addr + EXYNOS_SWRESET;
146 if (of_machine_is_compatible("samsung,exynos5440")) {
148 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
150 addr = of_iomap(np, 0) + 0xbc;
151 status = __raw_readl(addr);
153 addr = of_iomap(np, 0) + 0xcc;
154 val = __raw_readl(addr);
156 val = (val & 0xffff0000) | (status & 0xffff);
159 __raw_writel(val, addr);
162 static struct platform_device exynos_cpuidle = {
163 .name = "exynos_cpuidle",
164 .dev.platform_data = exynos_enter_aftr,
168 void __iomem *sysram_base_addr;
169 void __iomem *sysram_ns_base_addr;
171 void __init exynos_sysram_init(void)
173 struct device_node *node;
175 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
176 if (!of_device_is_available(node))
178 sysram_base_addr = of_iomap(node, 0);
182 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
183 if (!of_device_is_available(node))
185 sysram_ns_base_addr = of_iomap(node, 0);
190 static void __init exynos_init_late(void)
192 if (of_machine_is_compatible("samsung,exynos5440"))
193 /* to be supported later */
196 pm_genpd_poweroff_unused();
200 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
201 int depth, void *data)
203 struct map_desc iodesc;
207 if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
208 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
211 reg = of_get_flat_dt_prop(node, "reg", &len);
212 if (reg == NULL || len != (sizeof(unsigned long) * 2))
215 iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
216 iodesc.length = be32_to_cpu(reg[1]) - 1;
217 iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
218 iodesc.type = MT_DEVICE;
219 iotable_init(&iodesc, 1);
226 * register the standard cpu IO areas
228 static void __init exynos_map_io(void)
230 if (soc_is_exynos4())
231 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
233 if (soc_is_exynos5())
234 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
237 static void __init exynos_init_io(void)
241 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
243 /* detect cpu id and rev. */
244 s5p_init_cpu(S5P_VA_CHIPID);
249 static const struct of_device_id exynos_dt_pmu_match[] = {
250 { .compatible = "samsung,exynos3250-pmu" },
251 { .compatible = "samsung,exynos4210-pmu" },
252 { .compatible = "samsung,exynos4212-pmu" },
253 { .compatible = "samsung,exynos4412-pmu" },
254 { .compatible = "samsung,exynos5250-pmu" },
255 { .compatible = "samsung,exynos5260-pmu" },
256 { .compatible = "samsung,exynos5410-pmu" },
257 { .compatible = "samsung,exynos5420-pmu" },
261 static void exynos_map_pmu(void)
263 struct device_node *np;
265 np = of_find_matching_node(NULL, exynos_dt_pmu_match);
267 pmu_base_addr = of_iomap(np, 0);
270 panic("failed to find exynos pmu register\n");
273 static void __init exynos_init_irq(void)
277 * Since platsmp.c needs pmu base address by the time
278 * DT is not unflatten so we can't use DT APIs before
284 static void __init exynos_dt_machine_init(void)
286 struct device_node *i2c_np;
287 const char *i2c_compat = "samsung,s3c2440-i2c";
292 * Exynos5's legacy i2c controller and new high speed i2c
293 * controller have muxed interrupt sources. By default the
294 * interrupts for 4-channel HS-I2C controller are enabled.
295 * If node for first four channels of legacy i2c controller
296 * are available then re-configure the interrupts via the
299 if (soc_is_exynos5()) {
300 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
301 if (of_device_is_available(i2c_np)) {
302 id = of_alias_get_id(i2c_np, "i2c");
304 tmp = readl(EXYNOS5_SYS_I2C_CFG);
305 writel(tmp & ~(0x1 << id),
306 EXYNOS5_SYS_I2C_CFG);
313 * This is called from smp_prepare_cpus if we've built for SMP, but
314 * we still need to set it up for PM and firmware ops if not.
316 if (!IS_ENABLED(CONFIG_SMP))
317 exynos_sysram_init();
319 if (of_machine_is_compatible("samsung,exynos4210") ||
320 of_machine_is_compatible("samsung,exynos5250"))
321 platform_device_register(&exynos_cpuidle);
323 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
325 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
328 static char const *exynos_dt_compat[] __initconst = {
330 "samsung,exynos3250",
332 "samsung,exynos4210",
333 "samsung,exynos4212",
334 "samsung,exynos4412",
336 "samsung,exynos5250",
337 "samsung,exynos5260",
338 "samsung,exynos5420",
339 "samsung,exynos5440",
343 static void __init exynos_reserve(void)
345 #ifdef CONFIG_S5P_DEV_MFC
353 for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
354 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
359 static void __init exynos_dt_fixup(void)
362 * Some versions of uboot pass garbage entries in the memory node,
363 * use the old CONFIG_ARM_NR_BANKS
365 of_fdt_limit_memory(8);
368 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
369 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
370 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
371 .l2c_aux_val = 0x3c400001,
372 .l2c_aux_mask = 0xc20fffff,
373 .smp = smp_ops(exynos_smp_ops),
374 .map_io = exynos_init_io,
375 .init_early = exynos_firmware_init,
376 .init_irq = exynos_init_irq,
377 .init_machine = exynos_dt_machine_init,
378 .init_late = exynos_init_late,
379 .dt_compat = exynos_dt_compat,
380 .restart = exynos_restart,
381 .reserve = exynos_reserve,
382 .dt_fixup = exynos_dt_fixup,