2 * SAMSUNG EXYNOS Flattened Device Tree enabled machine
4 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/serial_s3c.h>
17 #include <linux/of_address.h>
18 #include <linux/of_fdt.h>
19 #include <linux/of_platform.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/arch.h>
26 #include <asm/mach/map.h>
27 #include <asm/memory.h>
35 static struct map_desc exynos4_iodesc[] __initdata = {
37 .virtual = (unsigned long)S3C_VA_SYS,
38 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
42 .virtual = (unsigned long)S3C_VA_TIMER,
43 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
47 .virtual = (unsigned long)S3C_VA_WATCHDOG,
48 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
52 .virtual = (unsigned long)S5P_VA_SROMC,
53 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
57 .virtual = (unsigned long)S5P_VA_SYSTIMER,
58 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
62 .virtual = (unsigned long)S5P_VA_PMU,
63 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
67 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
68 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
72 .virtual = (unsigned long)S5P_VA_GIC_CPU,
73 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
77 .virtual = (unsigned long)S5P_VA_GIC_DIST,
78 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
82 .virtual = (unsigned long)S5P_VA_CMU,
83 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
87 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
88 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
92 .virtual = (unsigned long)S5P_VA_L2CC,
93 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
97 .virtual = (unsigned long)S5P_VA_DMC0,
98 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
102 .virtual = (unsigned long)S5P_VA_DMC1,
103 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
107 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
108 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
114 static struct map_desc exynos4_iodesc0[] __initdata = {
116 .virtual = (unsigned long)S5P_VA_SYSRAM,
117 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
123 static struct map_desc exynos4_iodesc1[] __initdata = {
125 .virtual = (unsigned long)S5P_VA_SYSRAM,
126 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
132 static struct map_desc exynos4210_iodesc[] __initdata = {
134 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
135 .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
141 static struct map_desc exynos4x12_iodesc[] __initdata = {
143 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
144 .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
150 static struct map_desc exynos5250_iodesc[] __initdata = {
152 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
153 .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
159 static struct map_desc exynos5_iodesc[] __initdata = {
161 .virtual = (unsigned long)S3C_VA_SYS,
162 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
166 .virtual = (unsigned long)S3C_VA_TIMER,
167 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
171 .virtual = (unsigned long)S3C_VA_WATCHDOG,
172 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
176 .virtual = (unsigned long)S5P_VA_SROMC,
177 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
181 .virtual = (unsigned long)S5P_VA_SYSRAM,
182 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
186 .virtual = (unsigned long)S5P_VA_CMU,
187 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
188 .length = 144 * SZ_1K,
191 .virtual = (unsigned long)S5P_VA_PMU,
192 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
198 void exynos_restart(enum reboot_mode mode, const char *cmd)
200 struct device_node *np;
202 void __iomem *addr = EXYNOS_SWRESET;
204 if (of_machine_is_compatible("samsung,exynos5440")) {
206 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
208 addr = of_iomap(np, 0) + 0xbc;
209 status = __raw_readl(addr);
211 addr = of_iomap(np, 0) + 0xcc;
212 val = __raw_readl(addr);
214 val = (val & 0xffff0000) | (status & 0xffff);
217 __raw_writel(val, addr);
220 static struct platform_device exynos_cpuidle = {
221 .name = "exynos_cpuidle",
225 void __init exynos_cpuidle_init(void)
227 platform_device_register(&exynos_cpuidle);
230 void __init exynos_cpufreq_init(void)
232 platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
235 void __init exynos_init_late(void)
237 if (of_machine_is_compatible("samsung,exynos5440"))
238 /* to be supported later */
241 pm_genpd_poweroff_unused();
245 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
246 int depth, void *data)
248 struct map_desc iodesc;
252 if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
253 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
256 reg = of_get_flat_dt_prop(node, "reg", &len);
257 if (reg == NULL || len != (sizeof(unsigned long) * 2))
260 iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
261 iodesc.length = be32_to_cpu(reg[1]) - 1;
262 iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
263 iodesc.type = MT_DEVICE;
264 iotable_init(&iodesc, 1);
271 * register the standard cpu IO areas
273 static void __init exynos_map_io(void)
275 if (soc_is_exynos4())
276 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
278 if (soc_is_exynos5())
279 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
281 if (soc_is_exynos4210()) {
282 if (samsung_rev() == EXYNOS4210_REV_0)
283 iotable_init(exynos4_iodesc0,
284 ARRAY_SIZE(exynos4_iodesc0));
286 iotable_init(exynos4_iodesc1,
287 ARRAY_SIZE(exynos4_iodesc1));
288 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
290 if (soc_is_exynos4212() || soc_is_exynos4412())
291 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
292 if (soc_is_exynos5250())
293 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
296 void __init exynos_init_io(void)
300 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
302 /* detect cpu id and rev. */
303 s5p_init_cpu(S5P_VA_CHIPID);
308 struct bus_type exynos_subsys = {
309 .name = "exynos-core",
310 .dev_name = "exynos-core",
313 static int __init exynos_core_init(void)
315 return subsys_system_register(&exynos_subsys, NULL);
317 core_initcall(exynos_core_init);
319 static void __init exynos_dt_machine_init(void)
321 struct device_node *i2c_np;
322 const char *i2c_compat = "samsung,s3c2440-i2c";
327 * Exynos5's legacy i2c controller and new high speed i2c
328 * controller have muxed interrupt sources. By default the
329 * interrupts for 4-channel HS-I2C controller are enabled.
330 * If node for first four channels of legacy i2c controller
331 * are available then re-configure the interrupts via the
334 if (soc_is_exynos5()) {
335 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
336 if (of_device_is_available(i2c_np)) {
337 id = of_alias_get_id(i2c_np, "i2c");
339 tmp = readl(EXYNOS5_SYS_I2C_CFG);
340 writel(tmp & ~(0x1 << id),
341 EXYNOS5_SYS_I2C_CFG);
347 exynos_cpuidle_init();
348 exynos_cpufreq_init();
350 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
353 static char const *exynos_dt_compat[] __initconst = {
355 "samsung,exynos4210",
356 "samsung,exynos4212",
357 "samsung,exynos4412",
359 "samsung,exynos5250",
360 "samsung,exynos5420",
361 "samsung,exynos5440",
365 static void __init exynos_reserve(void)
367 #ifdef CONFIG_S5P_DEV_MFC
375 for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
376 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
381 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
382 /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
383 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
384 .l2c_aux_val = 0x3c400001,
385 .l2c_aux_mask = 0xc20fffff,
386 .smp = smp_ops(exynos_smp_ops),
387 .map_io = exynos_init_io,
388 .init_early = exynos_firmware_init,
389 .init_machine = exynos_dt_machine_init,
390 .init_late = exynos_init_late,
391 .dt_compat = exynos_dt_compat,
392 .restart = exynos_restart,
393 .reserve = exynos_reserve,