1 /* arch/arm/mach-exynos4/include/mach/entry-macro.S
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
5 * Low-level IRQ helper macros for EXYNOS4 platforms
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <mach/hardware.h>
14 #include <asm/hardware/gic.h>
19 .macro get_irqnr_preamble, base, tmp
22 mrc p15, 0, \base, c0, c0, 5
27 ldr \tmp, =gic_bank_offset
33 addeq \tmp, \tmp, \tmp
34 addne \tmp, \tmp, \tmp, LSL #1
36 1: ldr \base, =gic_cpu_base_addr
38 add \base, \base, \tmp
41 .macro arch_ret_to_user, tmp1, tmp2
45 * The interrupt numbering scheme is defined in the
46 * interrupt controller spec. To wit:
48 * Interrupts 0-15 are IPI
50 * 29-31 are local. We allow 30 to be used for the watchdog.
52 * 1021-1022 are reserved
53 * 1023 is "spurious" (no interrupt)
55 * For now, we ignore all local interrupts so only return an interrupt if it's
56 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
58 * A simple read from the controller will tell us the number of the highest
59 * priority enabled interrupt. We then just need to check whether it is in the
60 * valid range for an IRQ (30-1020 inclusive).
63 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
65 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
69 bic \irqnr, \irqstat, #0x1c00
75 addne \irqnr, \irqnr, #32
79 /* We assume that irqstat (the raw value of the IRQ acknowledge
80 * register) is preserved from the macro above.
81 * If there is an IPI, we immediately signal end of interrupt on the
82 * controller, since this requires the original irqstat value which
83 * we won't easily be able to recreate later.
86 .macro test_for_ipi, irqnr, irqstat, base, tmp
87 bic \irqnr, \irqstat, #0x1c00
89 strcc \irqstat, [\base, #GIC_CPU_EOI]