arch/arm/mach-exynos/mach-smdkv310.c

   1 /* linux/arch/arm/mach-exynos4/mach-smdkv310.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/serial_core.h>
  12 #include <linux/delay.h>
  13 #include <linux/gpio.h>
  14 #include <linux/lcd.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/smsc911x.h>
  18 #include <linux/io.h>
  19 #include <linux/i2c.h>
  20 #include <linux/input.h>
  21 #include <linux/pwm_backlight.h>
  22
  23 #include <asm/mach/arch.h>
  24 #include <asm/hardware/gic.h>
  25 #include <asm/mach-types.h>
  26
  27 #include <video/platform_lcd.h>
  28 #include <plat/regs-serial.h>
  29 #include <plat/regs-srom.h>
  30 #include <plat/regs-fb-v4.h>
  31 #include <plat/cpu.h>
  32 #include <plat/devs.h>
  33 #include <plat/fb.h>
  34 #include <plat/keypad.h>
  35 #include <plat/sdhci.h>
  36 #include <plat/iic.h>
  37 #include <plat/pd.h>
  38 #include <plat/gpio-cfg.h>
  39 #include <plat/backlight.h>
  40 #include <plat/mfc.h>
  41 #include <plat/ehci.h>
  42 #include <plat/clock.h>
  43
  44 #include <mach/map.h>
  45 #include <mach/ohci.h>
  46
  47 #include <drm/exynos_drm.h>
  48 #include "common.h"
  49
  50 /* Following are default values for UCON, ULCON and UFCON UART registers */
  51 #define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
  52                                  S3C2410_UCON_RXILEVEL |        \
  53                                  S3C2410_UCON_TXIRQMODE |       \
  54                                  S3C2410_UCON_RXIRQMODE |       \
  55                                  S3C2410_UCON_RXFIFO_TOI |      \
  56                                  S3C2443_UCON_RXERR_IRQEN)
  57
  58 #define SMDKV310_ULCON_DEFAULT  S3C2410_LCON_CS8
  59
  60 #define SMDKV310_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
  61                                  S5PV210_UFCON_TXTRIG4 |        \
  62                                  S5PV210_UFCON_RXTRIG4)
  63
  64 static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
  65         [0] = {
  66                 .hwport         = 0,
  67                 .flags          = 0,
  68                 .ucon           = SMDKV310_UCON_DEFAULT,
  69                 .ulcon          = SMDKV310_ULCON_DEFAULT,
  70                 .ufcon          = SMDKV310_UFCON_DEFAULT,
  71         },
  72         [1] = {
  73                 .hwport         = 1,
  74                 .flags          = 0,
  75                 .ucon           = SMDKV310_UCON_DEFAULT,
  76                 .ulcon          = SMDKV310_ULCON_DEFAULT,
  77                 .ufcon          = SMDKV310_UFCON_DEFAULT,
  78         },
  79         [2] = {
  80                 .hwport         = 2,
  81                 .flags          = 0,
  82                 .ucon           = SMDKV310_UCON_DEFAULT,
  83                 .ulcon          = SMDKV310_ULCON_DEFAULT,
  84                 .ufcon          = SMDKV310_UFCON_DEFAULT,
  85         },
  86         [3] = {
  87                 .hwport         = 3,
  88                 .flags          = 0,
  89                 .ucon           = SMDKV310_UCON_DEFAULT,
  90                 .ulcon          = SMDKV310_ULCON_DEFAULT,
  91                 .ufcon          = SMDKV310_UFCON_DEFAULT,
  92         },
  93 };
  94
  95 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
  96         .cd_type                = S3C_SDHCI_CD_INTERNAL,
  97         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
  98 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
  99         .max_width              = 8,
 100         .host_caps              = MMC_CAP_8_BIT_DATA,
 101 #endif
 102 };
 103
 104 static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
 105         .cd_type                = S3C_SDHCI_CD_GPIO,
 106         .ext_cd_gpio            = EXYNOS4_GPK0(2),
 107         .ext_cd_gpio_invert     = 1,
 108         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 109 };
 110
 111 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
 112         .cd_type                = S3C_SDHCI_CD_INTERNAL,
 113         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 114 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
 115         .max_width              = 8,
 116         .host_caps              = MMC_CAP_8_BIT_DATA,
 117 #endif
 118 };
 119
 120 static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
 121         .cd_type                = S3C_SDHCI_CD_GPIO,
 122         .ext_cd_gpio            = EXYNOS4_GPK2(2),
 123         .ext_cd_gpio_invert     = 1,
 124         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 125 };
 126
 127 static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
 128                                    unsigned int power)
 129 {
 130         if (power) {
 131 #if !defined(CONFIG_BACKLIGHT_PWM)
 132                 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
 133                 gpio_free(EXYNOS4_GPD0(1));
 134 #endif
 135                 /* fire nRESET on power up */
 136                 gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
 137                 mdelay(100);
 138
 139                 gpio_set_value(EXYNOS4_GPX0(6), 0);
 140                 mdelay(10);
 141
 142                 gpio_set_value(EXYNOS4_GPX0(6), 1);
 143                 mdelay(10);
 144
 145                 gpio_free(EXYNOS4_GPX0(6));
 146         } else {
 147 #if !defined(CONFIG_BACKLIGHT_PWM)
 148                 gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
 149                 gpio_free(EXYNOS4_GPD0(1));
 150 #endif
 151         }
 152 }
 153
 154 static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
 155         .set_power              = lcd_lte480wv_set_power,
 156 };
 157
 158 static struct platform_device smdkv310_lcd_lte480wv = {
 159         .name                   = "platform-lcd",
 160         .dev.parent             = &s5p_device_fimd0.dev,
 161         .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
 162 };
 163
 164 #ifdef CONFIG_DRM_EXYNOS
 165 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
 166         .panel  = {
 167                 .timing = {
 168                         .left_margin    = 13,
 169                         .right_margin   = 8,
 170                         .upper_margin   = 7,
 171                         .lower_margin   = 5,
 172                         .hsync_len      = 3,
 173                         .vsync_len      = 1,
 174                         .xres           = 800,
 175                         .yres           = 480,
 176                 },
 177         },
 178         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 179         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 180         .default_win    = 0,
 181         .bpp            = 32,
 182 };
 183 #else
 184 static struct s3c_fb_pd_win smdkv310_fb_win0 = {
 185         .win_mode = {
 186                 .left_margin    = 13,
 187                 .right_margin   = 8,
 188                 .upper_margin   = 7,
 189                 .lower_margin   = 5,
 190                 .hsync_len      = 3,
 191                 .vsync_len      = 1,
 192                 .xres           = 800,
 193                 .yres           = 480,
 194         },
 195         .max_bpp                = 32,
 196         .default_bpp            = 24,
 197 };
 198
 199 static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
 200         .win[0]         = &smdkv310_fb_win0,
 201         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
 202         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 203         .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 204 };
 205 #endif
 206
 207 static struct resource smdkv310_smsc911x_resources[] = {
 208         [0] = {
 209                 .start  = EXYNOS4_PA_SROM_BANK(1),
 210                 .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
 211                 .flags  = IORESOURCE_MEM,
 212         },
 213         [1] = {
 214                 .start  = IRQ_EINT(5),
 215                 .end    = IRQ_EINT(5),
 216                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
 217         },
 218 };
 219
 220 static struct smsc911x_platform_config smsc9215_config = {
 221         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
 222         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 223         .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
 224         .phy_interface  = PHY_INTERFACE_MODE_MII,
 225         .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
 226 };
 227
 228 static struct platform_device smdkv310_smsc911x = {
 229         .name           = "smsc911x",
 230         .id             = -1,
 231         .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
 232         .resource       = smdkv310_smsc911x_resources,
 233         .dev            = {
 234                 .platform_data  = &smsc9215_config,
 235         },
 236 };
 237
 238 static uint32_t smdkv310_keymap[] __initdata = {
 239         /* KEY(row, col, keycode) */
 240         KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
 241         KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
 242         KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
 243         KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
 244 };
 245
 246 static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
 247         .keymap         = smdkv310_keymap,
 248         .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
 249 };
 250
 251 static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
 252         .keymap_data    = &smdkv310_keymap_data,
 253         .rows           = 2,
 254         .cols           = 8,
 255 };
 256
 257 static struct i2c_board_info i2c_devs1[] __initdata = {
 258         {I2C_BOARD_INFO("wm8994", 0x1a),},
 259 };
 260
 261 /* USB EHCI */
 262 static struct s5p_ehci_platdata smdkv310_ehci_pdata;
 263
 264 static void __init smdkv310_ehci_init(void)
 265 {
 266         struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
 267
 268         s5p_ehci_set_platdata(pdata);
 269 }
 270
 271 /* USB OHCI */
 272 static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
 273
 274 static void __init smdkv310_ohci_init(void)
 275 {
 276         struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
 277
 278         exynos4_ohci_set_platdata(pdata);
 279 }
 280
 281 static struct platform_device *smdkv310_devices[] __initdata = {
 282         &s3c_device_hsmmc0,
 283         &s3c_device_hsmmc1,
 284         &s3c_device_hsmmc2,
 285         &s3c_device_hsmmc3,
 286         &s3c_device_i2c1,
 287         &s5p_device_i2c_hdmiphy,
 288         &s3c_device_rtc,
 289         &s3c_device_wdt,
 290         &s5p_device_ehci,
 291         &s5p_device_fimc0,
 292         &s5p_device_fimc1,
 293         &s5p_device_fimc2,
 294         &s5p_device_fimc3,
 295         &s5p_device_fimc_md,
 296         &s5p_device_g2d,
 297         &s5p_device_jpeg,
 298 #ifdef CONFIG_DRM_EXYNOS
 299         &exynos_device_drm,
 300 #endif
 301         &exynos4_device_ac97,
 302         &exynos4_device_i2s0,
 303         &exynos4_device_ohci,
 304         &samsung_device_keypad,
 305         &s5p_device_mfc,
 306         &s5p_device_mfc_l,
 307         &s5p_device_mfc_r,
 308         &exynos4_device_spdif,
 309         &exynos4_device_sysmmu,
 310         &samsung_asoc_dma,
 311         &samsung_asoc_idma,
 312         &s5p_device_fimd0,
 313         &smdkv310_lcd_lte480wv,
 314         &smdkv310_smsc911x,
 315         &exynos4_device_ahci,
 316         &s5p_device_hdmi,
 317         &s5p_device_mixer,
 318 };
 319
 320 static void __init smdkv310_smsc911x_init(void)
 321 {
 322         u32 cs1;
 323
 324         /* configure nCS1 width to 16 bits */
 325         cs1 = __raw_readl(S5P_SROM_BW) &
 326                 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
 327         cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
 328                 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
 329                 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
 330                 S5P_SROM_BW__NCS1__SHIFT;
 331         __raw_writel(cs1, S5P_SROM_BW);
 332
 333         /* set timing for nCS1 suitable for ethernet chip */
 334         __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
 335                      (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
 336                      (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
 337                      (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
 338                      (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
 339                      (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
 340                      (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
 341 }
 342
 343 /* LCD Backlight data */
 344 static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
 345         .no = EXYNOS4_GPD0(1),
 346         .func = S3C_GPIO_SFN(2),
 347 };
 348
 349 static struct platform_pwm_backlight_data smdkv310_bl_data = {
 350         .pwm_id = 1,
 351         .pwm_period_ns  = 1000,
 352 };
 353
 354 static void s5p_tv_setup(void)
 355 {
 356         /* direct HPD to HDMI chip */
 357         WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
 358         s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
 359         s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
 360 }
 361
 362 static void __init smdkv310_map_io(void)
 363 {
 364         exynos_init_io(NULL, 0);
 365         s3c24xx_init_clocks(24000000);
 366         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
 367 }
 368
 369 static void __init smdkv310_reserve(void)
 370 {
 371         s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
 372 }
 373
 374 static void __init smdkv310_machine_init(void)
 375 {
 376         s3c_i2c1_set_platdata(NULL);
 377         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 378
 379         smdkv310_smsc911x_init();
 380
 381         s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
 382         s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
 383         s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
 384         s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
 385
 386         s5p_tv_setup();
 387         s5p_i2c_hdmiphy_set_platdata(NULL);
 388
 389         samsung_keypad_set_platdata(&smdkv310_keypad_data);
 390
 391         samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
 392 #ifdef CONFIG_DRM_EXYNOS
 393         s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
 394         exynos4_fimd0_gpio_setup_24bpp();
 395 #else
 396         s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
 397 #endif
 398
 399         smdkv310_ehci_init();
 400         smdkv310_ohci_init();
 401         clk_xusbxti.rate = 24000000;
 402
 403         platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 404 }
 405
 406 MACHINE_START(SMDKV310, "SMDKV310")
 407         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 408         /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
 409         .atag_offset    = 0x100,
 410         .init_irq       = exynos4_init_irq,
 411         .map_io         = smdkv310_map_io,
 412         .handle_irq     = gic_handle_irq,
 413         .init_machine   = smdkv310_machine_init,
 414         .timer          = &exynos4_timer,
 415         .reserve        = &smdkv310_reserve,
 416         .restart        = exynos4_restart,
 417 MACHINE_END
 418
 419 MACHINE_START(SMDKC210, "SMDKC210")
 420         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 421         .atag_offset    = 0x100,
 422         .init_irq       = exynos4_init_irq,
 423         .map_io         = smdkv310_map_io,
 424         .handle_irq     = gic_handle_irq,
 425         .init_machine   = smdkv310_machine_init,
 426         .timer          = &exynos4_timer,
 427         .restart        = exynos4_restart,
 428 MACHINE_END