1 /* linux/arch/arm/mach-exynos4/mct.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 MCT(Multi-Core Timer) support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/percpu.h>
23 #include <asm/hardware/gic.h>
28 #include <mach/irqs.h>
29 #include <mach/regs-mct.h>
30 #include <asm/mach/time.h>
37 static unsigned long clk_cnt_per_tick;
38 static unsigned long clk_rate;
39 static unsigned int mct_int_type;
41 struct mct_clock_event_device {
42 struct clock_event_device *evt;
47 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
49 static void exynos4_mct_write(unsigned int value, void *addr)
51 void __iomem *stat_addr;
55 __raw_writel(value, addr);
57 if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
58 u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
59 switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
60 case (u32) MCT_L_TCON_OFFSET:
61 stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
62 mask = 1 << 3; /* L_TCON write status */
64 case (u32) MCT_L_ICNTB_OFFSET:
65 stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
66 mask = 1 << 1; /* L_ICNTB write status */
68 case (u32) MCT_L_TCNTB_OFFSET:
69 stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
70 mask = 1 << 0; /* L_TCNTB write status */
77 case (u32) EXYNOS4_MCT_G_TCON:
78 stat_addr = EXYNOS4_MCT_G_WSTAT;
79 mask = 1 << 16; /* G_TCON write status */
81 case (u32) EXYNOS4_MCT_G_COMP0_L:
82 stat_addr = EXYNOS4_MCT_G_WSTAT;
83 mask = 1 << 0; /* G_COMP0_L write status */
85 case (u32) EXYNOS4_MCT_G_COMP0_U:
86 stat_addr = EXYNOS4_MCT_G_WSTAT;
87 mask = 1 << 1; /* G_COMP0_U write status */
89 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
90 stat_addr = EXYNOS4_MCT_G_WSTAT;
91 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
93 case (u32) EXYNOS4_MCT_G_CNT_L:
94 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
95 mask = 1 << 0; /* G_CNT_L write status */
97 case (u32) EXYNOS4_MCT_G_CNT_U:
98 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
99 mask = 1 << 1; /* G_CNT_U write status */
106 /* Wait maximum 1 ms until written values are applied */
107 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
108 if (__raw_readl(stat_addr) & mask) {
109 __raw_writel(mask, stat_addr);
113 panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
116 /* Clocksource handling */
117 static void exynos4_mct_frc_start(u32 hi, u32 lo)
121 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
122 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
124 reg = __raw_readl(EXYNOS4_MCT_G_TCON);
125 reg |= MCT_G_TCON_START;
126 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
129 static cycle_t exynos4_frc_read(struct clocksource *cs)
132 u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
136 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
137 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
140 return ((cycle_t)hi << 32) | lo;
143 static void exynos4_frc_resume(struct clocksource *cs)
145 exynos4_mct_frc_start(0, 0);
148 struct clocksource mct_frc = {
151 .read = exynos4_frc_read,
152 .mask = CLOCKSOURCE_MASK(64),
153 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
154 .resume = exynos4_frc_resume,
157 static void __init exynos4_clocksource_init(void)
159 exynos4_mct_frc_start(0, 0);
161 if (clocksource_register_hz(&mct_frc, clk_rate))
162 panic("%s: can't register clocksource\n", mct_frc.name);
165 static void exynos4_mct_comp0_stop(void)
169 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
170 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
172 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
173 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
176 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
177 unsigned long cycles)
182 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
184 if (mode == CLOCK_EVT_MODE_PERIODIC) {
185 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
186 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
189 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
190 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
191 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
193 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
195 tcon |= MCT_G_TCON_COMP0_ENABLE;
196 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
199 static int exynos4_comp_set_next_event(unsigned long cycles,
200 struct clock_event_device *evt)
202 exynos4_mct_comp0_start(evt->mode, cycles);
207 static void exynos4_comp_set_mode(enum clock_event_mode mode,
208 struct clock_event_device *evt)
210 exynos4_mct_comp0_stop();
213 case CLOCK_EVT_MODE_PERIODIC:
214 exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
217 case CLOCK_EVT_MODE_ONESHOT:
218 case CLOCK_EVT_MODE_UNUSED:
219 case CLOCK_EVT_MODE_SHUTDOWN:
220 case CLOCK_EVT_MODE_RESUME:
225 static struct clock_event_device mct_comp_device = {
227 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
229 .set_next_event = exynos4_comp_set_next_event,
230 .set_mode = exynos4_comp_set_mode,
233 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
235 struct clock_event_device *evt = dev_id;
237 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
239 evt->event_handler(evt);
244 static struct irqaction mct_comp_event_irq = {
245 .name = "mct_comp_irq",
246 .flags = IRQF_TIMER | IRQF_IRQPOLL,
247 .handler = exynos4_mct_comp_isr,
248 .dev_id = &mct_comp_device,
251 static void exynos4_clockevent_init(void)
253 clk_cnt_per_tick = clk_rate / 2 / HZ;
255 clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
256 mct_comp_device.max_delta_ns =
257 clockevent_delta2ns(0xffffffff, &mct_comp_device);
258 mct_comp_device.min_delta_ns =
259 clockevent_delta2ns(0xf, &mct_comp_device);
260 mct_comp_device.cpumask = cpumask_of(0);
261 clockevents_register_device(&mct_comp_device);
263 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
266 #ifdef CONFIG_LOCAL_TIMERS
267 /* Clock event handling */
268 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
271 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
272 void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
274 tmp = __raw_readl(addr);
277 exynos4_mct_write(tmp, addr);
281 static void exynos4_mct_tick_start(unsigned long cycles,
282 struct mct_clock_event_device *mevt)
286 exynos4_mct_tick_stop(mevt);
288 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
290 /* update interrupt count buffer */
291 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
293 /* enable MCT tick interrupt */
294 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
296 tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
297 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
298 MCT_L_TCON_INTERVAL_MODE;
299 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
302 static int exynos4_tick_set_next_event(unsigned long cycles,
303 struct clock_event_device *evt)
305 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
307 exynos4_mct_tick_start(cycles, mevt);
312 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
313 struct clock_event_device *evt)
315 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
317 exynos4_mct_tick_stop(mevt);
320 case CLOCK_EVT_MODE_PERIODIC:
321 exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
324 case CLOCK_EVT_MODE_ONESHOT:
325 case CLOCK_EVT_MODE_UNUSED:
326 case CLOCK_EVT_MODE_SHUTDOWN:
327 case CLOCK_EVT_MODE_RESUME:
332 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
334 struct clock_event_device *evt = mevt->evt;
337 * This is for supporting oneshot mode.
338 * Mct would generate interrupt periodically
339 * without explicit stopping.
341 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
342 exynos4_mct_tick_stop(mevt);
344 /* Clear the MCT tick interrupt */
345 if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
346 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
353 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
355 struct mct_clock_event_device *mevt = dev_id;
356 struct clock_event_device *evt = mevt->evt;
358 exynos4_mct_tick_clear(mevt);
360 evt->event_handler(evt);
365 static struct irqaction mct_tick0_event_irq = {
366 .name = "mct_tick0_irq",
367 .flags = IRQF_TIMER | IRQF_NOBALANCING,
368 .handler = exynos4_mct_tick_isr,
371 static struct irqaction mct_tick1_event_irq = {
372 .name = "mct_tick1_irq",
373 .flags = IRQF_TIMER | IRQF_NOBALANCING,
374 .handler = exynos4_mct_tick_isr,
377 static void exynos4_mct_tick_init(struct clock_event_device *evt)
379 struct mct_clock_event_device *mevt;
380 unsigned int cpu = smp_processor_id();
382 mevt = this_cpu_ptr(&percpu_mct_tick);
385 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
386 sprintf(mevt->name, "mct_tick%d", cpu);
388 evt->name = mevt->name;
389 evt->cpumask = cpumask_of(cpu);
390 evt->set_next_event = exynos4_tick_set_next_event;
391 evt->set_mode = exynos4_tick_set_mode;
392 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
395 clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
397 clockevent_delta2ns(0x7fffffff, evt);
399 clockevent_delta2ns(0xf, evt);
401 clockevents_register_device(evt);
403 exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
405 if (mct_int_type == MCT_INT_SPI) {
407 mct_tick0_event_irq.dev_id = mevt;
408 evt->irq = IRQ_MCT_L0;
409 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
411 mct_tick1_event_irq.dev_id = mevt;
412 evt->irq = IRQ_MCT_L1;
413 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
414 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
417 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
421 /* Setup the local clock events for a CPU */
422 int __cpuinit local_timer_setup(struct clock_event_device *evt)
424 exynos4_mct_tick_init(evt);
429 void local_timer_stop(struct clock_event_device *evt)
431 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
432 if (mct_int_type == MCT_INT_SPI)
433 disable_irq(evt->irq);
435 disable_percpu_irq(IRQ_MCT_LOCALTIMER);
437 #endif /* CONFIG_LOCAL_TIMERS */
439 static void __init exynos4_timer_resources(void)
442 mct_clk = clk_get(NULL, "xtal");
444 clk_rate = clk_get_rate(mct_clk);
446 if (mct_int_type == MCT_INT_PPI) {
449 err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
450 exynos4_mct_tick_isr, "MCT",
452 WARN(err, "MCT: can't request IRQ %d (%d)\n",
453 IRQ_MCT_LOCALTIMER, err);
457 static void __init exynos4_timer_init(void)
459 if (soc_is_exynos4210())
460 mct_int_type = MCT_INT_SPI;
462 mct_int_type = MCT_INT_PPI;
464 exynos4_timer_resources();
465 exynos4_clocksource_init();
466 exynos4_clockevent_init();
469 struct sys_timer exynos4_timer = {
470 .init = exynos4_timer_init,