2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * Copyright (C) 2002 ARM Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
22 #include <linux/of_address.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_plat.h>
26 #include <asm/smp_scu.h>
27 #include <asm/firmware.h>
34 extern void exynos4_secondary_startup(void);
37 * exynos_core_power_down : power down the specified cpu
38 * @cpu : the cpu to power down
40 * Power down the specified cpu. The sequence must be finished by a
41 * call to cpu_do_idle()
44 void exynos_cpu_power_down(int cpu)
46 pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
50 * exynos_cpu_power_up : power up the specified cpu
51 * @cpu : the cpu to power up
53 * Power up the specified cpu
55 void exynos_cpu_power_up(int cpu)
57 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
58 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
62 * exynos_cpu_power_state : returns the power state of the cpu
63 * @cpu : the cpu to retrieve the power state from
66 int exynos_cpu_power_state(int cpu)
68 return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
69 S5P_CORE_LOCAL_PWR_EN);
73 * exynos_cluster_power_down : power down the specified cluster
74 * @cluster : the cluster to power down
76 void exynos_cluster_power_down(int cluster)
78 pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
82 * exynos_cluster_power_up : power up the specified cluster
83 * @cluster : the cluster to power up
85 void exynos_cluster_power_up(int cluster)
87 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
88 EXYNOS_COMMON_CONFIGURATION(cluster));
92 * exynos_cluster_power_state : returns the power state of the cluster
93 * @cluster : the cluster to retrieve the power state from
96 int exynos_cluster_power_state(int cluster)
98 return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
99 S5P_CORE_LOCAL_PWR_EN);
102 static inline void __iomem *cpu_boot_reg_base(void)
104 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
105 return pmu_base_addr + S5P_INFORM5;
106 return sysram_base_addr;
109 static inline void __iomem *cpu_boot_reg(int cpu)
111 void __iomem *boot_reg;
113 boot_reg = cpu_boot_reg_base();
115 return ERR_PTR(-ENODEV);
116 if (soc_is_exynos4412())
118 else if (soc_is_exynos5420() || soc_is_exynos5800())
124 * Write pen_release in a way that is guaranteed to be visible to all
125 * observers, irrespective of whether they're taking part in coherency
126 * or not. This is necessary for the hotplug code to work reliably.
128 static void write_pen_release(int val)
132 sync_cache_w(&pen_release);
135 static void __iomem *scu_base_addr(void)
137 return (void __iomem *)(S5P_VA_SCU);
140 static DEFINE_SPINLOCK(boot_lock);
142 static void exynos_secondary_init(unsigned int cpu)
145 * let the primary processor know we're out of the
146 * pen, then head off into the C entry point
148 write_pen_release(-1);
151 * Synchronise with the boot thread.
153 spin_lock(&boot_lock);
154 spin_unlock(&boot_lock);
157 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
159 unsigned long timeout;
160 u32 mpidr = cpu_logical_map(cpu);
161 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
165 * Set synchronisation state between this boot processor
166 * and the secondary one
168 spin_lock(&boot_lock);
171 * The secondary processor is waiting to be released from
172 * the holding pen - release it, then wait for it to flag
173 * that it has been released by resetting pen_release.
175 * Note that "pen_release" is the hardware CPU core ID, whereas
176 * "cpu" is Linux's internal ID.
178 write_pen_release(core_id);
180 if (!exynos_cpu_power_state(core_id)) {
181 exynos_cpu_power_up(core_id);
184 /* wait max 10 ms until cpu1 is on */
185 while (exynos_cpu_power_state(core_id)
186 != S5P_CORE_LOCAL_PWR_EN) {
194 printk(KERN_ERR "cpu1 power enable failed");
195 spin_unlock(&boot_lock);
200 * Send the secondary CPU a soft interrupt, thereby causing
201 * the boot monitor to read the system wide flags register,
202 * and branch to the address found there.
205 timeout = jiffies + (1 * HZ);
206 while (time_before(jiffies, timeout)) {
207 unsigned long boot_addr;
211 boot_addr = virt_to_phys(exynos4_secondary_startup);
214 * Try to set boot address using firmware first
215 * and fall back to boot register if it fails.
217 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
218 if (ret && ret != -ENOSYS)
220 if (ret == -ENOSYS) {
221 void __iomem *boot_reg = cpu_boot_reg(core_id);
223 if (IS_ERR(boot_reg)) {
224 ret = PTR_ERR(boot_reg);
227 __raw_writel(boot_addr, cpu_boot_reg(core_id));
230 call_firmware_op(cpu_boot, core_id);
232 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
234 if (pen_release == -1)
241 * now the secondary core is starting up let it run its
242 * calibrations, then wait for it to finish
245 spin_unlock(&boot_lock);
247 return pen_release != -1 ? ret : 0;
251 * Initialise the CPU possible map early - this describes the CPUs
252 * which may be present or become present in the system.
255 static void __init exynos_smp_init_cpus(void)
257 void __iomem *scu_base = scu_base_addr();
258 unsigned int i, ncores;
260 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
261 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
264 * CPU Nodes are passed thru DT and set_cpu_possible
265 * is set by "arm_dt_init_cpu_maps".
270 if (ncores > nr_cpu_ids) {
271 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
276 for (i = 0; i < ncores; i++)
277 set_cpu_possible(i, true);
280 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
284 exynos_sysram_init();
286 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
287 scu_enable(scu_base_addr());
290 * Write the address of secondary startup into the
291 * system-wide flags register. The boot monitor waits
292 * until it receives a soft interrupt, and then the
293 * secondary CPU branches to this address.
295 * Try using firmware operation first and fall back to
296 * boot register if it fails.
298 for (i = 1; i < max_cpus; ++i) {
299 unsigned long boot_addr;
304 mpidr = cpu_logical_map(i);
305 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
306 boot_addr = virt_to_phys(exynos4_secondary_startup);
308 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
309 if (ret && ret != -ENOSYS)
311 if (ret == -ENOSYS) {
312 void __iomem *boot_reg = cpu_boot_reg(core_id);
314 if (IS_ERR(boot_reg))
316 __raw_writel(boot_addr, cpu_boot_reg(core_id));
321 struct smp_operations exynos_smp_ops __initdata = {
322 .smp_init_cpus = exynos_smp_init_cpus,
323 .smp_prepare_cpus = exynos_smp_prepare_cpus,
324 .smp_secondary_init = exynos_secondary_init,
325 .smp_boot_secondary = exynos_boot_secondary,
326 #ifdef CONFIG_HOTPLUG_CPU
327 .cpu_die = exynos_cpu_die,