1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
23 #include <linux/of_address.h>
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
33 extern void exynos4_secondary_startup(void);
35 void __iomem *sysram_base_addr;
36 void __iomem *sysram_ns_base_addr;
38 static void __init exynos_smp_prepare_sysram(void)
40 struct device_node *node;
42 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
43 if (!of_device_is_available(node))
45 sysram_base_addr = of_iomap(node, 0);
49 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
50 if (!of_device_is_available(node))
52 sysram_ns_base_addr = of_iomap(node, 0);
57 static inline void __iomem *cpu_boot_reg_base(void)
59 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
61 return sysram_base_addr;
64 static inline void __iomem *cpu_boot_reg(int cpu)
66 void __iomem *boot_reg;
68 boot_reg = cpu_boot_reg_base();
70 return ERR_PTR(-ENODEV);
71 if (soc_is_exynos4412())
73 else if (soc_is_exynos5420() || soc_is_exynos5800())
79 * Write pen_release in a way that is guaranteed to be visible to all
80 * observers, irrespective of whether they're taking part in coherency
81 * or not. This is necessary for the hotplug code to work reliably.
83 static void write_pen_release(int val)
87 sync_cache_w(&pen_release);
90 static void __iomem *scu_base_addr(void)
92 return (void __iomem *)(S5P_VA_SCU);
95 static DEFINE_SPINLOCK(boot_lock);
97 static void exynos_secondary_init(unsigned int cpu)
100 * let the primary processor know we're out of the
101 * pen, then head off into the C entry point
103 write_pen_release(-1);
106 * Synchronise with the boot thread.
108 spin_lock(&boot_lock);
109 spin_unlock(&boot_lock);
112 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
114 unsigned long timeout;
115 unsigned long phys_cpu = cpu_logical_map(cpu);
119 * Set synchronisation state between this boot processor
120 * and the secondary one
122 spin_lock(&boot_lock);
125 * The secondary processor is waiting to be released from
126 * the holding pen - release it, then wait for it to flag
127 * that it has been released by resetting pen_release.
129 * Note that "pen_release" is the hardware CPU ID, whereas
130 * "cpu" is Linux's internal ID.
132 write_pen_release(phys_cpu);
134 if (!exynos_cpu_power_state(cpu)) {
135 exynos_cpu_power_up(cpu);
138 /* wait max 10 ms until cpu1 is on */
139 while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
147 printk(KERN_ERR "cpu1 power enable failed");
148 spin_unlock(&boot_lock);
153 * Send the secondary CPU a soft interrupt, thereby causing
154 * the boot monitor to read the system wide flags register,
155 * and branch to the address found there.
158 timeout = jiffies + (1 * HZ);
159 while (time_before(jiffies, timeout)) {
160 unsigned long boot_addr;
164 boot_addr = virt_to_phys(exynos4_secondary_startup);
167 * Try to set boot address using firmware first
168 * and fall back to boot register if it fails.
170 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
171 if (ret && ret != -ENOSYS)
173 if (ret == -ENOSYS) {
174 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
176 if (IS_ERR(boot_reg)) {
177 ret = PTR_ERR(boot_reg);
180 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
183 call_firmware_op(cpu_boot, phys_cpu);
185 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
187 if (pen_release == -1)
194 * now the secondary core is starting up let it run its
195 * calibrations, then wait for it to finish
198 spin_unlock(&boot_lock);
200 return pen_release != -1 ? ret : 0;
204 * Initialise the CPU possible map early - this describes the CPUs
205 * which may be present or become present in the system.
208 static void __init exynos_smp_init_cpus(void)
210 void __iomem *scu_base = scu_base_addr();
211 unsigned int i, ncores;
213 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
214 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
217 * CPU Nodes are passed thru DT and set_cpu_possible
218 * is set by "arm_dt_init_cpu_maps".
223 if (ncores > nr_cpu_ids) {
224 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
229 for (i = 0; i < ncores; i++)
230 set_cpu_possible(i, true);
233 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
237 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
238 scu_enable(scu_base_addr());
240 exynos_smp_prepare_sysram();
243 * Write the address of secondary startup into the
244 * system-wide flags register. The boot monitor waits
245 * until it receives a soft interrupt, and then the
246 * secondary CPU branches to this address.
248 * Try using firmware operation first and fall back to
249 * boot register if it fails.
251 for (i = 1; i < max_cpus; ++i) {
252 unsigned long phys_cpu;
253 unsigned long boot_addr;
256 phys_cpu = cpu_logical_map(i);
257 boot_addr = virt_to_phys(exynos4_secondary_startup);
259 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
260 if (ret && ret != -ENOSYS)
262 if (ret == -ENOSYS) {
263 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
265 if (IS_ERR(boot_reg))
267 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
272 struct smp_operations exynos_smp_ops __initdata = {
273 .smp_init_cpus = exynos_smp_init_cpus,
274 .smp_prepare_cpus = exynos_smp_prepare_cpus,
275 .smp_secondary_init = exynos_secondary_init,
276 .smp_boot_secondary = exynos_boot_secondary,
277 #ifdef CONFIG_HOTPLUG_CPU
278 .cpu_die = exynos_cpu_die,