1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
23 #include <linux/of_address.h>
25 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
33 extern void exynos4_secondary_startup(void);
35 static inline void __iomem *cpu_boot_reg_base(void)
37 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
39 return sysram_base_addr;
42 static inline void __iomem *cpu_boot_reg(int cpu)
44 void __iomem *boot_reg;
46 boot_reg = cpu_boot_reg_base();
48 return ERR_PTR(-ENODEV);
49 if (soc_is_exynos4412())
51 else if (soc_is_exynos5420() || soc_is_exynos5800())
57 * Write pen_release in a way that is guaranteed to be visible to all
58 * observers, irrespective of whether they're taking part in coherency
59 * or not. This is necessary for the hotplug code to work reliably.
61 static void write_pen_release(int val)
65 sync_cache_w(&pen_release);
68 static void __iomem *scu_base_addr(void)
70 return (void __iomem *)(S5P_VA_SCU);
73 static DEFINE_SPINLOCK(boot_lock);
75 static void exynos_secondary_init(unsigned int cpu)
78 * let the primary processor know we're out of the
79 * pen, then head off into the C entry point
81 write_pen_release(-1);
84 * Synchronise with the boot thread.
86 spin_lock(&boot_lock);
87 spin_unlock(&boot_lock);
90 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
92 unsigned long timeout;
93 u32 mpidr = cpu_logical_map(cpu);
94 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
98 * Set synchronisation state between this boot processor
99 * and the secondary one
101 spin_lock(&boot_lock);
104 * The secondary processor is waiting to be released from
105 * the holding pen - release it, then wait for it to flag
106 * that it has been released by resetting pen_release.
108 * Note that "pen_release" is the hardware CPU core ID, whereas
109 * "cpu" is Linux's internal ID.
111 write_pen_release(core_id);
113 if (!exynos_cpu_power_state(core_id)) {
114 exynos_cpu_power_up(core_id);
117 /* wait max 10 ms until cpu1 is on */
118 while (exynos_cpu_power_state(core_id)
119 != S5P_CORE_LOCAL_PWR_EN) {
127 printk(KERN_ERR "cpu1 power enable failed");
128 spin_unlock(&boot_lock);
133 * Send the secondary CPU a soft interrupt, thereby causing
134 * the boot monitor to read the system wide flags register,
135 * and branch to the address found there.
138 timeout = jiffies + (1 * HZ);
139 while (time_before(jiffies, timeout)) {
140 unsigned long boot_addr;
144 boot_addr = virt_to_phys(exynos4_secondary_startup);
147 * Try to set boot address using firmware first
148 * and fall back to boot register if it fails.
150 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
151 if (ret && ret != -ENOSYS)
153 if (ret == -ENOSYS) {
154 void __iomem *boot_reg = cpu_boot_reg(core_id);
156 if (IS_ERR(boot_reg)) {
157 ret = PTR_ERR(boot_reg);
160 __raw_writel(boot_addr, cpu_boot_reg(core_id));
163 call_firmware_op(cpu_boot, core_id);
165 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
167 if (pen_release == -1)
174 * now the secondary core is starting up let it run its
175 * calibrations, then wait for it to finish
178 spin_unlock(&boot_lock);
180 return pen_release != -1 ? ret : 0;
184 * Initialise the CPU possible map early - this describes the CPUs
185 * which may be present or become present in the system.
188 static void __init exynos_smp_init_cpus(void)
190 void __iomem *scu_base = scu_base_addr();
191 unsigned int i, ncores;
193 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
194 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
197 * CPU Nodes are passed thru DT and set_cpu_possible
198 * is set by "arm_dt_init_cpu_maps".
203 if (ncores > nr_cpu_ids) {
204 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
209 for (i = 0; i < ncores; i++)
210 set_cpu_possible(i, true);
213 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
217 exynos_sysram_init();
219 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
220 scu_enable(scu_base_addr());
223 * Write the address of secondary startup into the
224 * system-wide flags register. The boot monitor waits
225 * until it receives a soft interrupt, and then the
226 * secondary CPU branches to this address.
228 * Try using firmware operation first and fall back to
229 * boot register if it fails.
231 for (i = 1; i < max_cpus; ++i) {
232 unsigned long boot_addr;
237 mpidr = cpu_logical_map(i);
238 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
239 boot_addr = virt_to_phys(exynos4_secondary_startup);
241 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
242 if (ret && ret != -ENOSYS)
244 if (ret == -ENOSYS) {
245 void __iomem *boot_reg = cpu_boot_reg(core_id);
247 if (IS_ERR(boot_reg))
249 __raw_writel(boot_addr, cpu_boot_reg(core_id));
254 struct smp_operations exynos_smp_ops __initdata = {
255 .smp_init_cpus = exynos_smp_init_cpus,
256 .smp_prepare_cpus = exynos_smp_prepare_cpus,
257 .smp_secondary_init = exynos_secondary_init,
258 .smp_boot_secondary = exynos_boot_secondary,
259 #ifdef CONFIG_HOTPLUG_CPU
260 .cpu_die = exynos_cpu_die,