2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Power Management support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irqchip/arm-gic.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <asm/cacheflush.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/smp_scu.h>
28 #include <asm/suspend.h>
30 #include <plat/pm-common.h>
32 #include <plat/regs-srom.h>
40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
41 * @hwirq: Hardware IRQ signal of the GIC
42 * @mask: Mask in PMU wake-up mask register
44 struct exynos_wkup_irq {
49 static struct sleep_save exynos5_sys_save[] = {
50 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
53 static struct sleep_save exynos_core_save[] = {
55 SAVE_ITEM(S5P_SROM_BW),
56 SAVE_ITEM(S5P_SROM_BC0),
57 SAVE_ITEM(S5P_SROM_BC1),
58 SAVE_ITEM(S5P_SROM_BC2),
59 SAVE_ITEM(S5P_SROM_BC3),
66 static u32 exynos_irqwake_intmask = 0xffffffff;
68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
69 { 76, BIT(1) }, /* RTC alarm */
70 { 77, BIT(2) }, /* RTC tick */
74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
75 { 75, BIT(1) }, /* RTC alarm */
76 { 76, BIT(2) }, /* RTC tick */
80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
82 const struct exynos_wkup_irq *wkup_irq;
84 if (soc_is_exynos5250())
85 wkup_irq = exynos5250_wkup_irq;
87 wkup_irq = exynos4_wkup_irq;
89 while (wkup_irq->mask) {
90 if (wkup_irq->hwirq == data->hwirq) {
92 exynos_irqwake_intmask |= wkup_irq->mask;
94 exynos_irqwake_intmask &= ~wkup_irq->mask;
104 * exynos_core_power_down : power down the specified cpu
105 * @cpu : the cpu to power down
107 * Power down the specified cpu. The sequence must be finished by a
108 * call to cpu_do_idle()
111 void exynos_cpu_power_down(int cpu)
113 __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
117 * exynos_cpu_power_up : power up the specified cpu
118 * @cpu : the cpu to power up
120 * Power up the specified cpu
122 void exynos_cpu_power_up(int cpu)
124 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
125 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
129 * exynos_cpu_power_state : returns the power state of the cpu
130 * @cpu : the cpu to retrieve the power state from
133 int exynos_cpu_power_state(int cpu)
135 return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
136 S5P_CORE_LOCAL_PWR_EN);
140 * exynos_cluster_power_down : power down the specified cluster
141 * @cluster : the cluster to power down
143 void exynos_cluster_power_down(int cluster)
145 __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
149 * exynos_cluster_power_up : power up the specified cluster
150 * @cluster : the cluster to power up
152 void exynos_cluster_power_up(int cluster)
154 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
155 EXYNOS_COMMON_CONFIGURATION(cluster));
159 * exynos_cluster_power_state : returns the power state of the cluster
160 * @cluster : the cluster to retrieve the power state from
163 int exynos_cluster_power_state(int cluster)
165 return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
166 S5P_CORE_LOCAL_PWR_EN);
169 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
170 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
171 (sysram_base_addr + 0x24) : S5P_INFORM0))
172 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
173 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
174 (sysram_base_addr + 0x20) : S5P_INFORM1))
176 #define S5P_CHECK_AFTR 0xFCBA0D10
177 #define S5P_CHECK_SLEEP 0x00000BAD
179 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
180 static void exynos_set_wakeupmask(long mask)
182 __raw_writel(mask, S5P_WAKEUP_MASK);
185 static void exynos_cpu_set_boot_vector(long flags)
187 __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
188 __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
191 void exynos_enter_aftr(void)
193 exynos_set_wakeupmask(0x0000ff3e);
194 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
195 /* Set value of power down register for aftr mode */
196 exynos_sys_powerdown_conf(SYS_AFTR);
199 /* For Cortex-A9 Diagnostic and Power control register */
200 static unsigned int save_arm_register[2];
202 static void exynos_cpu_save_register(void)
206 /* Save Power control register */
207 asm ("mrc p15, 0, %0, c15, c0, 0"
208 : "=r" (tmp) : : "cc");
210 save_arm_register[0] = tmp;
212 /* Save Diagnostic register */
213 asm ("mrc p15, 0, %0, c15, c0, 1"
214 : "=r" (tmp) : : "cc");
216 save_arm_register[1] = tmp;
219 static void exynos_cpu_restore_register(void)
223 /* Restore Power control register */
224 tmp = save_arm_register[0];
226 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
230 /* Restore Diagnostic register */
231 tmp = save_arm_register[1];
233 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
238 static int exynos_cpu_suspend(unsigned long arg)
240 #ifdef CONFIG_CACHE_L2X0
244 if (soc_is_exynos5250())
247 /* issue the standby signal into the pm unit. */
250 pr_info("Failed to suspend the system\n");
251 return 1; /* Aborting suspend */
254 static void exynos_pm_prepare(void)
258 /* Set wake-up mask registers */
259 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
260 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
262 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
264 if (soc_is_exynos5250()) {
265 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
266 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
267 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
268 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
269 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
272 /* Set value of power down register for sleep mode */
274 exynos_sys_powerdown_conf(SYS_SLEEP);
275 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
277 /* ensure at least INFORM0 has the resume address */
279 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
282 static void exynos_pm_central_suspend(void)
286 /* Setting Central Sequence Register for power down mode */
287 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
288 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
289 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
292 static int exynos_pm_suspend(void)
296 exynos_pm_central_suspend();
298 /* Setting SEQ_OPTION register */
300 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
301 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
303 if (!soc_is_exynos5250())
304 exynos_cpu_save_register();
309 static int exynos_pm_central_resume(void)
314 * If PMU failed while entering sleep mode, WFI will be
315 * ignored by PMU and then exiting cpu_do_idle().
316 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
319 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
320 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
321 tmp |= S5P_CENTRAL_LOWPWR_CFG;
322 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
323 /* clear the wakeup state register */
324 __raw_writel(0x0, S5P_WAKEUP_STAT);
325 /* No need to perform below restore code */
332 static void exynos_pm_resume(void)
334 if (exynos_pm_central_resume())
337 if (!soc_is_exynos5250())
338 exynos_cpu_restore_register();
340 /* For release retention */
342 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
343 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
344 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
345 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
346 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
347 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
348 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
350 if (soc_is_exynos5250())
351 s3c_pm_do_restore(exynos5_sys_save,
352 ARRAY_SIZE(exynos5_sys_save));
354 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
356 if (!soc_is_exynos5250())
357 scu_enable(S5P_VA_SCU);
361 /* Clear SLEEP mode set in INFORM1 */
362 __raw_writel(0x0, S5P_INFORM1);
367 static struct syscore_ops exynos_pm_syscore_ops = {
368 .suspend = exynos_pm_suspend,
369 .resume = exynos_pm_resume,
376 static int exynos_suspend_enter(suspend_state_t state)
382 S3C_PMDBG("%s: suspending the system...\n", __func__);
384 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
385 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
387 if (exynos_irqwake_intmask == -1U
388 && exynos_get_eint_wake_mask() == -1U) {
389 pr_err("%s: No wake-up sources!\n", __func__);
390 pr_err("%s: Aborting sleep\n", __func__);
397 s3c_pm_check_store();
399 ret = cpu_suspend(0, exynos_cpu_suspend);
403 s3c_pm_restore_uarts();
405 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
406 __raw_readl(S5P_WAKEUP_STAT));
408 s3c_pm_check_restore();
410 S3C_PMDBG("%s: resuming the system...\n", __func__);
415 static int exynos_suspend_prepare(void)
417 s3c_pm_check_prepare();
422 static void exynos_suspend_finish(void)
424 s3c_pm_check_cleanup();
427 static const struct platform_suspend_ops exynos_suspend_ops = {
428 .enter = exynos_suspend_enter,
429 .prepare = exynos_suspend_prepare,
430 .finish = exynos_suspend_finish,
431 .valid = suspend_valid_only_mem,
434 static int exynos_cpu_pm_notifier(struct notifier_block *self,
435 unsigned long cmd, void *v)
437 int cpu = smp_processor_id();
442 exynos_pm_central_suspend();
443 exynos_cpu_save_register();
449 if (!soc_is_exynos5250())
450 scu_enable(S5P_VA_SCU);
451 exynos_cpu_restore_register();
452 exynos_pm_central_resume();
460 static struct notifier_block exynos_cpu_pm_notifier_block = {
461 .notifier_call = exynos_cpu_pm_notifier,
464 void __init exynos_pm_init(void)
468 cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
470 /* Platform-specific GIC callback */
471 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
473 /* All wakeup disable */
474 tmp = __raw_readl(S5P_WAKEUP_MASK);
475 tmp |= ((0xFF << 8) | (0x1F << 1));
476 __raw_writel(tmp, S5P_WAKEUP_MASK);
478 register_syscore_ops(&exynos_pm_syscore_ops);
479 suspend_set_ops(&exynos_suspend_ops);