2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Power Management support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irqchip/arm-gic.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <asm/cacheflush.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/smp_scu.h>
28 #include <asm/suspend.h>
30 #include <plat/pm-common.h>
31 #include <plat/regs-srom.h>
40 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
41 * @hwirq: Hardware IRQ signal of the GIC
42 * @mask: Mask in PMU wake-up mask register
44 struct exynos_wkup_irq {
49 static struct sleep_save exynos5_sys_save[] = {
50 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
53 static struct sleep_save exynos_core_save[] = {
55 SAVE_ITEM(S5P_SROM_BW),
56 SAVE_ITEM(S5P_SROM_BC0),
57 SAVE_ITEM(S5P_SROM_BC1),
58 SAVE_ITEM(S5P_SROM_BC2),
59 SAVE_ITEM(S5P_SROM_BC3),
66 static u32 exynos_irqwake_intmask = 0xffffffff;
68 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
69 { 76, BIT(1) }, /* RTC alarm */
70 { 77, BIT(2) }, /* RTC tick */
74 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
75 { 75, BIT(1) }, /* RTC alarm */
76 { 76, BIT(2) }, /* RTC tick */
80 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
82 const struct exynos_wkup_irq *wkup_irq;
84 if (soc_is_exynos5250())
85 wkup_irq = exynos5250_wkup_irq;
87 wkup_irq = exynos4_wkup_irq;
89 while (wkup_irq->mask) {
90 if (wkup_irq->hwirq == data->hwirq) {
92 exynos_irqwake_intmask |= wkup_irq->mask;
94 exynos_irqwake_intmask &= ~wkup_irq->mask;
103 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
104 pmu_base_addr + S5P_INFORM7 : \
105 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
106 (sysram_base_addr + 0x24) : \
107 pmu_base_addr + S5P_INFORM0))
108 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
109 pmu_base_addr + S5P_INFORM6 : \
110 (samsung_rev() == EXYNOS4210_REV_1_0 ? \
111 (sysram_base_addr + 0x20) : \
112 pmu_base_addr + S5P_INFORM1))
114 #define S5P_CHECK_AFTR 0xFCBA0D10
115 #define S5P_CHECK_SLEEP 0x00000BAD
117 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
118 static void exynos_set_wakeupmask(long mask)
120 pmu_raw_writel(mask, S5P_WAKEUP_MASK);
123 static void exynos_cpu_set_boot_vector(long flags)
125 __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
126 __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
129 void exynos_enter_aftr(void)
131 exynos_set_wakeupmask(0x0000ff3e);
132 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
133 /* Set value of power down register for aftr mode */
134 exynos_sys_powerdown_conf(SYS_AFTR);
137 /* For Cortex-A9 Diagnostic and Power control register */
138 static unsigned int save_arm_register[2];
140 static void exynos_cpu_save_register(void)
144 /* Save Power control register */
145 asm ("mrc p15, 0, %0, c15, c0, 0"
146 : "=r" (tmp) : : "cc");
148 save_arm_register[0] = tmp;
150 /* Save Diagnostic register */
151 asm ("mrc p15, 0, %0, c15, c0, 1"
152 : "=r" (tmp) : : "cc");
154 save_arm_register[1] = tmp;
157 static void exynos_cpu_restore_register(void)
161 /* Restore Power control register */
162 tmp = save_arm_register[0];
164 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
168 /* Restore Diagnostic register */
169 tmp = save_arm_register[1];
171 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
176 static int exynos_cpu_suspend(unsigned long arg)
178 #ifdef CONFIG_CACHE_L2X0
182 if (soc_is_exynos5250())
185 /* issue the standby signal into the pm unit. */
188 pr_info("Failed to suspend the system\n");
189 return 1; /* Aborting suspend */
192 static void exynos_pm_prepare(void)
196 /* Set wake-up mask registers */
197 pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
198 pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
200 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
202 if (soc_is_exynos5250()) {
203 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
204 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
205 tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
206 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
207 pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
210 /* Set value of power down register for sleep mode */
212 exynos_sys_powerdown_conf(SYS_SLEEP);
213 pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
215 /* ensure at least INFORM0 has the resume address */
217 pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
220 static void exynos_pm_central_suspend(void)
224 /* Setting Central Sequence Register for power down mode */
225 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
226 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
227 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
230 static int exynos_pm_suspend(void)
234 exynos_pm_central_suspend();
236 /* Setting SEQ_OPTION register */
238 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
239 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
241 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
242 exynos_cpu_save_register();
247 static int exynos_pm_central_resume(void)
252 * If PMU failed while entering sleep mode, WFI will be
253 * ignored by PMU and then exiting cpu_do_idle().
254 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
257 tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
258 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
259 tmp |= S5P_CENTRAL_LOWPWR_CFG;
260 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
261 /* clear the wakeup state register */
262 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
263 /* No need to perform below restore code */
270 static void exynos_pm_resume(void)
272 if (exynos_pm_central_resume())
275 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
276 exynos_cpu_restore_register();
278 /* For release retention */
280 pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
281 pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
282 pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
283 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
284 pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
285 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
286 pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
288 if (soc_is_exynos5250())
289 s3c_pm_do_restore(exynos5_sys_save,
290 ARRAY_SIZE(exynos5_sys_save));
292 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
294 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
295 scu_enable(S5P_VA_SCU);
299 /* Clear SLEEP mode set in INFORM1 */
300 pmu_raw_writel(0x0, S5P_INFORM1);
305 static struct syscore_ops exynos_pm_syscore_ops = {
306 .suspend = exynos_pm_suspend,
307 .resume = exynos_pm_resume,
314 static int exynos_suspend_enter(suspend_state_t state)
320 S3C_PMDBG("%s: suspending the system...\n", __func__);
322 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
323 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
325 if (exynos_irqwake_intmask == -1U
326 && exynos_get_eint_wake_mask() == -1U) {
327 pr_err("%s: No wake-up sources!\n", __func__);
328 pr_err("%s: Aborting sleep\n", __func__);
335 s3c_pm_check_store();
337 ret = cpu_suspend(0, exynos_cpu_suspend);
341 s3c_pm_restore_uarts();
343 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
344 pmu_raw_readl(S5P_WAKEUP_STAT));
346 s3c_pm_check_restore();
348 S3C_PMDBG("%s: resuming the system...\n", __func__);
353 static int exynos_suspend_prepare(void)
355 s3c_pm_check_prepare();
360 static void exynos_suspend_finish(void)
362 s3c_pm_check_cleanup();
365 static const struct platform_suspend_ops exynos_suspend_ops = {
366 .enter = exynos_suspend_enter,
367 .prepare = exynos_suspend_prepare,
368 .finish = exynos_suspend_finish,
369 .valid = suspend_valid_only_mem,
372 static int exynos_cpu_pm_notifier(struct notifier_block *self,
373 unsigned long cmd, void *v)
375 int cpu = smp_processor_id();
380 exynos_pm_central_suspend();
381 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
382 exynos_cpu_save_register();
388 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
389 scu_enable(S5P_VA_SCU);
390 exynos_cpu_restore_register();
392 exynos_pm_central_resume();
400 static struct notifier_block exynos_cpu_pm_notifier_block = {
401 .notifier_call = exynos_cpu_pm_notifier,
404 void __init exynos_pm_init(void)
408 cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
410 /* Platform-specific GIC callback */
411 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
413 /* All wakeup disable */
414 tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
415 tmp |= ((0xFF << 8) | (0x1F << 1));
416 pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
418 register_syscore_ops(&exynos_pm_syscore_ops);
419 suspend_set_ops(&exynos_suspend_ops);