2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
3 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <mach/regs-pmu.h>
18 #include <mach/regs-usb-phy.h>
20 #include <plat/usb-phy.h>
22 static atomic_t host_usage;
24 static int exynos4_usb_host_phy_is_on(void)
26 return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
29 static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
31 struct clk *xusbxti_clk;
34 xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
35 if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
36 if (soc_is_exynos4210()) {
37 /* set clock frequency for PLL */
38 phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
40 switch (clk_get_rate(xusbxti_clk)) {
42 phyclk |= EXYNOS4210_CLKSEL_12M;
45 phyclk |= EXYNOS4210_CLKSEL_48M;
49 phyclk |= EXYNOS4210_CLKSEL_24M;
52 writel(phyclk, EXYNOS4_PHYCLK);
53 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
54 /* set clock frequency for PLL */
55 phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
57 switch (clk_get_rate(xusbxti_clk)) {
59 phyclk |= EXYNOS4X12_CLKSEL_9600K;
62 phyclk |= EXYNOS4X12_CLKSEL_10M;
65 phyclk |= EXYNOS4X12_CLKSEL_12M;
68 phyclk |= EXYNOS4X12_CLKSEL_19200K;
71 phyclk |= EXYNOS4X12_CLKSEL_20M;
75 /* default reference clock */
76 phyclk |= EXYNOS4X12_CLKSEL_24M;
79 writel(phyclk, EXYNOS4_PHYCLK);
85 static int exynos4210_usb_phy0_init(struct platform_device *pdev)
89 writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
90 S5P_USBDEVICE_PHY_CONTROL);
92 exynos4210_usb_phy_clkset(pdev);
94 /* set to normal PHY0 */
95 writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
97 /* reset PHY0 and Link */
98 rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
99 writel(rstcon, EXYNOS4_RSTCON);
102 rstcon &= ~PHY0_SWRST_MASK;
103 writel(rstcon, EXYNOS4_RSTCON);
108 static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
110 writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
111 PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
113 writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
114 S5P_USBDEVICE_PHY_CONTROL);
119 static int exynos4210_usb_phy1_init(struct platform_device *pdev)
125 atomic_inc(&host_usage);
127 otg_clk = clk_get(&pdev->dev, "otg");
128 if (IS_ERR(otg_clk)) {
129 dev_err(&pdev->dev, "Failed to get otg clock\n");
130 return PTR_ERR(otg_clk);
133 err = clk_enable(otg_clk);
139 if (exynos4_usb_host_phy_is_on())
142 writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
143 S5P_USBHOST_PHY_CONTROL);
145 exynos4210_usb_phy_clkset(pdev);
147 /* floating prevention logic: disable */
148 writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
150 /* set to normal HSIC 0 and 1 of PHY1 */
151 writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
154 /* set to normal standard USB of PHY1 */
155 writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
157 /* reset all ports of both PHY and Link */
158 rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
160 writel(rstcon, EXYNOS4_RSTCON);
163 rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
164 writel(rstcon, EXYNOS4_RSTCON);
167 clk_disable(otg_clk);
173 static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
178 if (atomic_dec_return(&host_usage) > 0)
181 otg_clk = clk_get(&pdev->dev, "otg");
182 if (IS_ERR(otg_clk)) {
183 dev_err(&pdev->dev, "Failed to get otg clock\n");
184 return PTR_ERR(otg_clk);
187 err = clk_enable(otg_clk);
193 writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
196 writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
197 S5P_USBHOST_PHY_CONTROL);
199 clk_disable(otg_clk);
205 int s5p_usb_phy_init(struct platform_device *pdev, int type)
207 if (type == S5P_USB_PHY_DEVICE)
208 return exynos4210_usb_phy0_init(pdev);
209 else if (type == S5P_USB_PHY_HOST)
210 return exynos4210_usb_phy1_init(pdev);
215 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
217 if (type == S5P_USB_PHY_DEVICE)
218 return exynos4210_usb_phy0_exit(pdev);
219 else if (type == S5P_USB_PHY_HOST)
220 return exynos4210_usb_phy1_exit(pdev);