arch/arm/mach-exynos/suspend.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Suspend support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/cpu_pm.h>
  20 #include <linux/io.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25 #include <linux/err.h>
  26 #include <linux/regulator/machine.h>
  27
  28 #include <asm/cacheflush.h>
  29 #include <asm/hardware/cache-l2x0.h>
  30 #include <asm/firmware.h>
  31 #include <asm/mcpm.h>
  32 #include <asm/smp_scu.h>
  33 #include <asm/suspend.h>
  34
  35 #include <mach/map.h>
  36
  37 #include <plat/pm-common.h>
  38
  39 #include "common.h"
  40 #include "exynos-pmu.h"
  41 #include "regs-pmu.h"
  42
  43 #define REG_TABLE_END (-1U)
  44
  45 #define EXYNOS5420_CPU_STATE    0x28
  46
  47 /**
  48  * struct exynos_wkup_irq - PMU IRQ to mask mapping
  49  * @hwirq: Hardware IRQ signal of the PMU
  50  * @mask: Mask in PMU wake-up mask register
  51  */
  52 struct exynos_wkup_irq {
  53         unsigned int hwirq;
  54         u32 mask;
  55 };
  56
  57 struct exynos_pm_data {
  58         const struct exynos_wkup_irq *wkup_irq;
  59         unsigned int wake_disable_mask;
  60         unsigned int *release_ret_regs;
  61
  62         void (*pm_prepare)(void);
  63         void (*pm_resume_prepare)(void);
  64         void (*pm_resume)(void);
  65         int (*pm_suspend)(void);
  66         int (*cpu_suspend)(unsigned long);
  67 };
  68
  69 static const struct exynos_pm_data *pm_data;
  70
  71 static int exynos5420_cpu_state;
  72 static unsigned int exynos_pmu_spare3;
  73
  74 /*
  75  * GIC wake-up support
  76  */
  77
  78 static u32 exynos_irqwake_intmask = 0xffffffff;
  79
  80 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
  81         { 73, BIT(1) }, /* RTC alarm */
  82         { 74, BIT(2) }, /* RTC tick */
  83         { /* sentinel */ },
  84 };
  85
  86 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
  87         { 44, BIT(1) }, /* RTC alarm */
  88         { 45, BIT(2) }, /* RTC tick */
  89         { /* sentinel */ },
  90 };
  91
  92 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
  93         { 43, BIT(1) }, /* RTC alarm */
  94         { 44, BIT(2) }, /* RTC tick */
  95         { /* sentinel */ },
  96 };
  97
  98 static unsigned int exynos_release_ret_regs[] = {
  99         S5P_PAD_RET_MAUDIO_OPTION,
 100         S5P_PAD_RET_GPIO_OPTION,
 101         S5P_PAD_RET_UART_OPTION,
 102         S5P_PAD_RET_MMCA_OPTION,
 103         S5P_PAD_RET_MMCB_OPTION,
 104         S5P_PAD_RET_EBIA_OPTION,
 105         S5P_PAD_RET_EBIB_OPTION,
 106         REG_TABLE_END,
 107 };
 108
 109 static unsigned int exynos3250_release_ret_regs[] = {
 110         S5P_PAD_RET_MAUDIO_OPTION,
 111         S5P_PAD_RET_GPIO_OPTION,
 112         S5P_PAD_RET_UART_OPTION,
 113         S5P_PAD_RET_MMCA_OPTION,
 114         S5P_PAD_RET_MMCB_OPTION,
 115         S5P_PAD_RET_EBIA_OPTION,
 116         S5P_PAD_RET_EBIB_OPTION,
 117         S5P_PAD_RET_MMC2_OPTION,
 118         S5P_PAD_RET_SPI_OPTION,
 119         REG_TABLE_END,
 120 };
 121
 122 static unsigned int exynos5420_release_ret_regs[] = {
 123         EXYNOS_PAD_RET_DRAM_OPTION,
 124         EXYNOS_PAD_RET_MAUDIO_OPTION,
 125         EXYNOS_PAD_RET_JTAG_OPTION,
 126         EXYNOS5420_PAD_RET_GPIO_OPTION,
 127         EXYNOS5420_PAD_RET_UART_OPTION,
 128         EXYNOS5420_PAD_RET_MMCA_OPTION,
 129         EXYNOS5420_PAD_RET_MMCB_OPTION,
 130         EXYNOS5420_PAD_RET_MMCC_OPTION,
 131         EXYNOS5420_PAD_RET_HSI_OPTION,
 132         EXYNOS_PAD_RET_EBIA_OPTION,
 133         EXYNOS_PAD_RET_EBIB_OPTION,
 134         EXYNOS5420_PAD_RET_SPI_OPTION,
 135         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
 136         REG_TABLE_END,
 137 };
 138
 139 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 140 {
 141         const struct exynos_wkup_irq *wkup_irq;
 142
 143         if (!pm_data->wkup_irq)
 144                 return -ENOENT;
 145         wkup_irq = pm_data->wkup_irq;
 146
 147         while (wkup_irq->mask) {
 148                 if (wkup_irq->hwirq == data->hwirq) {
 149                         if (!state)
 150                                 exynos_irqwake_intmask |= wkup_irq->mask;
 151                         else
 152                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
 153                         return 0;
 154                 }
 155                 ++wkup_irq;
 156         }
 157
 158         return -ENOENT;
 159 }
 160
 161 static struct irq_chip exynos_pmu_chip = {
 162         .name                   = "PMU",
 163         .irq_eoi                = irq_chip_eoi_parent,
 164         .irq_mask               = irq_chip_mask_parent,
 165         .irq_unmask             = irq_chip_unmask_parent,
 166         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 167         .irq_set_wake           = exynos_irq_set_wake,
 168 #ifdef CONFIG_SMP
 169         .irq_set_affinity       = irq_chip_set_affinity_parent,
 170 #endif
 171 };
 172
 173 static int exynos_pmu_domain_xlate(struct irq_domain *domain,
 174                                    struct device_node *controller,
 175                                    const u32 *intspec,
 176                                    unsigned int intsize,
 177                                    unsigned long *out_hwirq,
 178                                    unsigned int *out_type)
 179 {
 180         if (domain->of_node != controller)
 181                 return -EINVAL; /* Shouldn't happen, really... */
 182         if (intsize != 3)
 183                 return -EINVAL; /* Not GIC compliant */
 184         if (intspec[0] != 0)
 185                 return -EINVAL; /* No PPI should point to this domain */
 186
 187         *out_hwirq = intspec[1];
 188         *out_type = intspec[2];
 189         return 0;
 190 }
 191
 192 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
 193                                    unsigned int virq,
 194                                    unsigned int nr_irqs, void *data)
 195 {
 196         struct of_phandle_args *args = data;
 197         struct of_phandle_args parent_args;
 198         irq_hw_number_t hwirq;
 199         int i;
 200
 201         if (args->args_count != 3)
 202                 return -EINVAL; /* Not GIC compliant */
 203         if (args->args[0] != 0)
 204                 return -EINVAL; /* No PPI should point to this domain */
 205
 206         hwirq = args->args[1];
 207
 208         for (i = 0; i < nr_irqs; i++)
 209                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 210                                               &exynos_pmu_chip, NULL);
 211
 212         parent_args = *args;
 213         parent_args.np = domain->parent->of_node;
 214         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
 215 }
 216
 217 static const struct irq_domain_ops exynos_pmu_domain_ops = {
 218         .xlate  = exynos_pmu_domain_xlate,
 219         .alloc  = exynos_pmu_domain_alloc,
 220         .free   = irq_domain_free_irqs_common,
 221 };
 222
 223 static int __init exynos_pmu_irq_init(struct device_node *node,
 224                                       struct device_node *parent)
 225 {
 226         struct irq_domain *parent_domain, *domain;
 227
 228         if (!parent) {
 229                 pr_err("%s: no parent, giving up\n", node->full_name);
 230                 return -ENODEV;
 231         }
 232
 233         parent_domain = irq_find_host(parent);
 234         if (!parent_domain) {
 235                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
 236                 return -ENXIO;
 237         }
 238
 239         pmu_base_addr = of_iomap(node, 0);
 240
 241         if (!pmu_base_addr) {
 242                 pr_err("%s: failed to find exynos pmu register\n",
 243                        node->full_name);
 244                 return -ENOMEM;
 245         }
 246
 247         domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
 248                                           node, &exynos_pmu_domain_ops,
 249                                           NULL);
 250         if (!domain) {
 251                 iounmap(pmu_base_addr);
 252                 return -ENOMEM;
 253         }
 254
 255         return 0;
 256 }
 257
 258 #define EXYNOS_PMU_IRQ(symbol, name)    IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
 259
 260 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
 261 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
 262 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
 263 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
 264 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
 265 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
 266 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
 267
 268 static int exynos_cpu_do_idle(void)
 269 {
 270         /* issue the standby signal into the pm unit. */
 271         cpu_do_idle();
 272
 273         pr_info("Failed to suspend the system\n");
 274         return 1; /* Aborting suspend */
 275 }
 276 static void exynos_flush_cache_all(void)
 277 {
 278         flush_cache_all();
 279         outer_flush_all();
 280 }
 281
 282 static int exynos_cpu_suspend(unsigned long arg)
 283 {
 284         exynos_flush_cache_all();
 285         return exynos_cpu_do_idle();
 286 }
 287
 288 static int exynos3250_cpu_suspend(unsigned long arg)
 289 {
 290         flush_cache_all();
 291         return exynos_cpu_do_idle();
 292 }
 293
 294 static int exynos5420_cpu_suspend(unsigned long arg)
 295 {
 296         /* MCPM works with HW CPU identifiers */
 297         unsigned int mpidr = read_cpuid_mpidr();
 298         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 299         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 300
 301         __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 302
 303         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 304                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
 305                 mcpm_cpu_suspend();
 306         }
 307
 308         pr_info("Failed to suspend the system\n");
 309
 310         /* return value != 0 means failure */
 311         return 1;
 312 }
 313
 314 static void exynos_pm_set_wakeup_mask(void)
 315 {
 316         /* Set wake-up mask registers */
 317         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
 318         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 319 }
 320
 321 static void exynos_pm_enter_sleep_mode(void)
 322 {
 323         /* Set value of power down register for sleep mode */
 324         exynos_sys_powerdown_conf(SYS_SLEEP);
 325         pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
 326 }
 327
 328 static void exynos_pm_prepare(void)
 329 {
 330         exynos_set_delayed_reset_assertion(false);
 331
 332         /* Set wake-up mask registers */
 333         exynos_pm_set_wakeup_mask();
 334
 335         exynos_pm_enter_sleep_mode();
 336
 337         /* ensure at least INFORM0 has the resume address */
 338         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 339 }
 340
 341 static void exynos3250_pm_prepare(void)
 342 {
 343         unsigned int tmp;
 344
 345         /* Set wake-up mask registers */
 346         exynos_pm_set_wakeup_mask();
 347
 348         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
 349         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 350         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
 351
 352         exynos_pm_enter_sleep_mode();
 353
 354         /* ensure at least INFORM0 has the resume address */
 355         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 356 }
 357
 358 static void exynos5420_pm_prepare(void)
 359 {
 360         unsigned int tmp;
 361
 362         /* Set wake-up mask registers */
 363         exynos_pm_set_wakeup_mask();
 364
 365         exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
 366         /*
 367          * The cpu state needs to be saved and restored so that the
 368          * secondary CPUs will enter low power start. Though the U-Boot
 369          * is setting the cpu state with low power flag, the kernel
 370          * needs to restore it back in case, the primary cpu fails to
 371          * suspend for any reason.
 372          */
 373         exynos5420_cpu_state = __raw_readl(sysram_base_addr +
 374                                                 EXYNOS5420_CPU_STATE);
 375
 376         exynos_pm_enter_sleep_mode();
 377
 378         /* ensure at least INFORM0 has the resume address */
 379         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 380                 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
 381
 382         tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
 383         tmp &= ~EXYNOS5_USE_RETENTION;
 384         pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
 385
 386         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 387         tmp |= EXYNOS5420_UFS;
 388         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 389
 390         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
 391         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
 392         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
 393
 394         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 395         tmp |= EXYNOS5420_EMULATION;
 396         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 397
 398         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 399         tmp |= EXYNOS5420_EMULATION;
 400         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 401 }
 402
 403
 404 static int exynos_pm_suspend(void)
 405 {
 406         exynos_pm_central_suspend();
 407
 408         /* Setting SEQ_OPTION register */
 409         pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
 410                        S5P_CENTRAL_SEQ_OPTION);
 411
 412         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 413                 exynos_cpu_save_register();
 414
 415         return 0;
 416 }
 417
 418 static int exynos5420_pm_suspend(void)
 419 {
 420         u32 this_cluster;
 421
 422         exynos_pm_central_suspend();
 423
 424         /* Setting SEQ_OPTION register */
 425
 426         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
 427         if (!this_cluster)
 428                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
 429                                 S5P_CENTRAL_SEQ_OPTION);
 430         else
 431                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
 432                                 S5P_CENTRAL_SEQ_OPTION);
 433         return 0;
 434 }
 435
 436 static void exynos_pm_release_retention(void)
 437 {
 438         unsigned int i;
 439
 440         for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
 441                 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
 442                                 pm_data->release_ret_regs[i]);
 443 }
 444
 445 static void exynos_pm_resume(void)
 446 {
 447         u32 cpuid = read_cpuid_part();
 448
 449         if (exynos_pm_central_resume())
 450                 goto early_wakeup;
 451
 452         /* For release retention */
 453         exynos_pm_release_retention();
 454
 455         if (cpuid == ARM_CPU_PART_CORTEX_A9)
 456                 scu_enable(S5P_VA_SCU);
 457
 458         if (call_firmware_op(resume) == -ENOSYS
 459             && cpuid == ARM_CPU_PART_CORTEX_A9)
 460                 exynos_cpu_restore_register();
 461
 462 early_wakeup:
 463
 464         /* Clear SLEEP mode set in INFORM1 */
 465         pmu_raw_writel(0x0, S5P_INFORM1);
 466         exynos_set_delayed_reset_assertion(true);
 467 }
 468
 469 static void exynos3250_pm_resume(void)
 470 {
 471         u32 cpuid = read_cpuid_part();
 472
 473         if (exynos_pm_central_resume())
 474                 goto early_wakeup;
 475
 476         /* For release retention */
 477         exynos_pm_release_retention();
 478
 479         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
 480
 481         if (call_firmware_op(resume) == -ENOSYS
 482             && cpuid == ARM_CPU_PART_CORTEX_A9)
 483                 exynos_cpu_restore_register();
 484
 485 early_wakeup:
 486
 487         /* Clear SLEEP mode set in INFORM1 */
 488         pmu_raw_writel(0x0, S5P_INFORM1);
 489 }
 490
 491 static void exynos5420_prepare_pm_resume(void)
 492 {
 493         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
 494                 WARN_ON(mcpm_cpu_powered_up());
 495 }
 496
 497 static void exynos5420_pm_resume(void)
 498 {
 499         unsigned long tmp;
 500
 501         /* Restore the CPU0 low power state register */
 502         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 503         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
 504                 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 505
 506         /* Restore the sysram cpu state register */
 507         __raw_writel(exynos5420_cpu_state,
 508                 sysram_base_addr + EXYNOS5420_CPU_STATE);
 509
 510         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 511                         S5P_CENTRAL_SEQ_OPTION);
 512
 513         if (exynos_pm_central_resume())
 514                 goto early_wakeup;
 515
 516         /* For release retention */
 517         exynos_pm_release_retention();
 518
 519         pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
 520
 521 early_wakeup:
 522
 523         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
 524         tmp &= ~EXYNOS5420_UFS;
 525         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
 526
 527         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
 528         tmp &= ~EXYNOS5420_EMULATION;
 529         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
 530
 531         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
 532         tmp &= ~EXYNOS5420_EMULATION;
 533         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
 534
 535         /* Clear SLEEP mode set in INFORM1 */
 536         pmu_raw_writel(0x0, S5P_INFORM1);
 537 }
 538
 539 /*
 540  * Suspend Ops
 541  */
 542
 543 static int exynos_suspend_enter(suspend_state_t state)
 544 {
 545         int ret;
 546
 547         s3c_pm_debug_init();
 548
 549         S3C_PMDBG("%s: suspending the system...\n", __func__);
 550
 551         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
 552                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
 553
 554         if (exynos_irqwake_intmask == -1U
 555             && exynos_get_eint_wake_mask() == -1U) {
 556                 pr_err("%s: No wake-up sources!\n", __func__);
 557                 pr_err("%s: Aborting sleep\n", __func__);
 558                 return -EINVAL;
 559         }
 560
 561         s3c_pm_save_uarts();
 562         if (pm_data->pm_prepare)
 563                 pm_data->pm_prepare();
 564         flush_cache_all();
 565         s3c_pm_check_store();
 566
 567         ret = call_firmware_op(suspend);
 568         if (ret == -ENOSYS)
 569                 ret = cpu_suspend(0, pm_data->cpu_suspend);
 570         if (ret)
 571                 return ret;
 572
 573         if (pm_data->pm_resume_prepare)
 574                 pm_data->pm_resume_prepare();
 575         s3c_pm_restore_uarts();
 576
 577         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
 578                         pmu_raw_readl(S5P_WAKEUP_STAT));
 579
 580         s3c_pm_check_restore();
 581
 582         S3C_PMDBG("%s: resuming the system...\n", __func__);
 583
 584         return 0;
 585 }
 586
 587 static int exynos_suspend_prepare(void)
 588 {
 589         int ret;
 590
 591         /*
 592          * REVISIT: It would be better if struct platform_suspend_ops
 593          * .prepare handler get the suspend_state_t as a parameter to
 594          * avoid hard-coding the suspend to mem state. It's safe to do
 595          * it now only because the suspend_valid_only_mem function is
 596          * used as the .valid callback used to check if a given state
 597          * is supported by the platform anyways.
 598          */
 599         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
 600         if (ret) {
 601                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
 602                 return ret;
 603         }
 604
 605         s3c_pm_check_prepare();
 606
 607         return 0;
 608 }
 609
 610 static void exynos_suspend_finish(void)
 611 {
 612         int ret;
 613
 614         s3c_pm_check_cleanup();
 615
 616         ret = regulator_suspend_finish();
 617         if (ret)
 618                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
 619 }
 620
 621 static const struct platform_suspend_ops exynos_suspend_ops = {
 622         .enter          = exynos_suspend_enter,
 623         .prepare        = exynos_suspend_prepare,
 624         .finish         = exynos_suspend_finish,
 625         .valid          = suspend_valid_only_mem,
 626 };
 627
 628 static const struct exynos_pm_data exynos3250_pm_data = {
 629         .wkup_irq       = exynos3250_wkup_irq,
 630         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 631         .release_ret_regs = exynos3250_release_ret_regs,
 632         .pm_suspend     = exynos_pm_suspend,
 633         .pm_resume      = exynos3250_pm_resume,
 634         .pm_prepare     = exynos3250_pm_prepare,
 635         .cpu_suspend    = exynos3250_cpu_suspend,
 636 };
 637
 638 static const struct exynos_pm_data exynos4_pm_data = {
 639         .wkup_irq       = exynos4_wkup_irq,
 640         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 641         .release_ret_regs = exynos_release_ret_regs,
 642         .pm_suspend     = exynos_pm_suspend,
 643         .pm_resume      = exynos_pm_resume,
 644         .pm_prepare     = exynos_pm_prepare,
 645         .cpu_suspend    = exynos_cpu_suspend,
 646 };
 647
 648 static const struct exynos_pm_data exynos5250_pm_data = {
 649         .wkup_irq       = exynos5250_wkup_irq,
 650         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
 651         .release_ret_regs = exynos_release_ret_regs,
 652         .pm_suspend     = exynos_pm_suspend,
 653         .pm_resume      = exynos_pm_resume,
 654         .pm_prepare     = exynos_pm_prepare,
 655         .cpu_suspend    = exynos_cpu_suspend,
 656 };
 657
 658 static const struct exynos_pm_data exynos5420_pm_data = {
 659         .wkup_irq       = exynos5250_wkup_irq,
 660         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
 661         .release_ret_regs = exynos5420_release_ret_regs,
 662         .pm_resume_prepare = exynos5420_prepare_pm_resume,
 663         .pm_resume      = exynos5420_pm_resume,
 664         .pm_suspend     = exynos5420_pm_suspend,
 665         .pm_prepare     = exynos5420_pm_prepare,
 666         .cpu_suspend    = exynos5420_cpu_suspend,
 667 };
 668
 669 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
 670         {
 671                 .compatible = "samsung,exynos3250-pmu",
 672                 .data = &exynos3250_pm_data,
 673         }, {
 674                 .compatible = "samsung,exynos4210-pmu",
 675                 .data = &exynos4_pm_data,
 676         }, {
 677                 .compatible = "samsung,exynos4212-pmu",
 678                 .data = &exynos4_pm_data,
 679         }, {
 680                 .compatible = "samsung,exynos4412-pmu",
 681                 .data = &exynos4_pm_data,
 682         }, {
 683                 .compatible = "samsung,exynos5250-pmu",
 684                 .data = &exynos5250_pm_data,
 685         }, {
 686                 .compatible = "samsung,exynos5420-pmu",
 687                 .data = &exynos5420_pm_data,
 688         },
 689         { /*sentinel*/ },
 690 };
 691
 692 static struct syscore_ops exynos_pm_syscore_ops;
 693
 694 void __init exynos_pm_init(void)
 695 {
 696         const struct of_device_id *match;
 697         struct device_node *np;
 698         u32 tmp;
 699
 700         np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
 701         if (!np) {
 702                 pr_err("Failed to find PMU node\n");
 703                 return;
 704         }
 705
 706         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
 707                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
 708                 return;
 709         }
 710
 711         pm_data = (const struct exynos_pm_data *) match->data;
 712
 713         /* All wakeup disable */
 714         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
 715         tmp |= pm_data->wake_disable_mask;
 716         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
 717
 718         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
 719         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
 720
 721         register_syscore_ops(&exynos_pm_syscore_ops);
 722         suspend_set_ops(&exynos_suspend_ops);
 723 }