1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
25 #include <mach/regs-clock.h>
27 static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m",
33 static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
38 static struct clk clk_sclk_usbphy0 = {
39 .name = "sclk_usbphy0",
44 static struct clk clk_sclk_usbphy1 = {
45 .name = "sclk_usbphy1",
49 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
54 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
59 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
64 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
69 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
74 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
79 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
84 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
89 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
94 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
99 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
104 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
109 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
114 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
119 /* Core list of CMU_CPU side */
121 static struct clksrc_clk clk_mout_apll = {
126 .sources = &clk_src_apll,
127 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
130 static struct clksrc_clk clk_sclk_apll = {
134 .parent = &clk_mout_apll.clk,
136 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
139 static struct clksrc_clk clk_mout_epll = {
144 .sources = &clk_src_epll,
145 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
148 static struct clksrc_clk clk_mout_mpll = {
153 .sources = &clk_src_mpll,
154 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
157 static struct clk *clkset_moutcore_list[] = {
158 [0] = &clk_mout_apll.clk,
159 [1] = &clk_mout_mpll.clk,
162 static struct clksrc_sources clkset_moutcore = {
163 .sources = clkset_moutcore_list,
164 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
167 static struct clksrc_clk clk_moutcore = {
172 .sources = &clkset_moutcore,
173 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
176 static struct clksrc_clk clk_coreclk = {
180 .parent = &clk_moutcore.clk,
182 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
185 static struct clksrc_clk clk_armclk = {
189 .parent = &clk_coreclk.clk,
193 static struct clksrc_clk clk_aclk_corem0 = {
195 .name = "aclk_corem0",
197 .parent = &clk_coreclk.clk,
199 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
202 static struct clksrc_clk clk_aclk_cores = {
204 .name = "aclk_cores",
206 .parent = &clk_coreclk.clk,
208 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
211 static struct clksrc_clk clk_aclk_corem1 = {
213 .name = "aclk_corem1",
215 .parent = &clk_coreclk.clk,
217 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
220 static struct clksrc_clk clk_periphclk = {
224 .parent = &clk_coreclk.clk,
226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
229 /* Core list of CMU_CORE side */
231 static struct clk *clkset_corebus_list[] = {
232 [0] = &clk_mout_mpll.clk,
233 [1] = &clk_sclk_apll.clk,
236 static struct clksrc_sources clkset_mout_corebus = {
237 .sources = clkset_corebus_list,
238 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
241 static struct clksrc_clk clk_mout_corebus = {
243 .name = "mout_corebus",
246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
250 static struct clksrc_clk clk_sclk_dmc = {
254 .parent = &clk_mout_corebus.clk,
256 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
259 static struct clksrc_clk clk_aclk_cored = {
261 .name = "aclk_cored",
263 .parent = &clk_sclk_dmc.clk,
265 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
268 static struct clksrc_clk clk_aclk_corep = {
270 .name = "aclk_corep",
272 .parent = &clk_aclk_cored.clk,
274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
277 static struct clksrc_clk clk_aclk_acp = {
281 .parent = &clk_mout_corebus.clk,
283 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
286 static struct clksrc_clk clk_pclk_acp = {
290 .parent = &clk_aclk_acp.clk,
292 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
295 /* Core list of CMU_TOP side */
297 static struct clk *clkset_aclk_top_list[] = {
298 [0] = &clk_mout_mpll.clk,
299 [1] = &clk_sclk_apll.clk,
302 static struct clksrc_sources clkset_aclk = {
303 .sources = clkset_aclk_top_list,
304 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
307 static struct clksrc_clk clk_aclk_200 = {
312 .sources = &clkset_aclk,
313 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
314 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
317 static struct clksrc_clk clk_aclk_100 = {
322 .sources = &clkset_aclk,
323 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
324 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
327 static struct clksrc_clk clk_aclk_160 = {
332 .sources = &clkset_aclk,
333 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
334 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
337 static struct clksrc_clk clk_aclk_133 = {
342 .sources = &clkset_aclk,
343 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
344 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
347 static struct clk *clkset_vpllsrc_list[] = {
349 [1] = &clk_sclk_hdmi27m,
352 static struct clksrc_sources clkset_vpllsrc = {
353 .sources = clkset_vpllsrc_list,
354 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
357 static struct clksrc_clk clk_vpllsrc = {
361 .enable = exynos4_clksrc_mask_top_ctrl,
364 .sources = &clkset_vpllsrc,
365 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
368 static struct clk *clkset_sclk_vpll_list[] = {
369 [0] = &clk_vpllsrc.clk,
370 [1] = &clk_fout_vpll,
373 static struct clksrc_sources clkset_sclk_vpll = {
374 .sources = clkset_sclk_vpll_list,
375 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
378 static struct clksrc_clk clk_sclk_vpll = {
383 .sources = &clkset_sclk_vpll,
384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
387 static struct clk init_clocks_off[] = {
391 .parent = &clk_aclk_100.clk,
392 .enable = exynos4_clk_ip_peril_ctrl,
397 .enable = exynos4_clk_ip_cam_ctrl,
402 .enable = exynos4_clk_ip_cam_ctrl,
407 .enable = exynos4_clk_ip_cam_ctrl,
412 .enable = exynos4_clk_ip_cam_ctrl,
417 .enable = exynos4_clk_ip_cam_ctrl,
422 .enable = exynos4_clk_ip_cam_ctrl,
427 .enable = exynos4_clk_ip_lcd0_ctrl,
432 .enable = exynos4_clk_ip_lcd1_ctrl,
437 .parent = &clk_aclk_133.clk,
438 .enable = exynos4_clk_ip_fsys_ctrl,
443 .parent = &clk_aclk_133.clk,
444 .enable = exynos4_clk_ip_fsys_ctrl,
449 .parent = &clk_aclk_133.clk,
450 .enable = exynos4_clk_ip_fsys_ctrl,
455 .parent = &clk_aclk_133.clk,
456 .enable = exynos4_clk_ip_fsys_ctrl,
461 .parent = &clk_aclk_133.clk,
462 .enable = exynos4_clk_ip_fsys_ctrl,
467 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10),
472 .enable = exynos4_clk_ip_fsys_ctrl,
477 .enable = exynos4_clk_ip_fsys_ctrl,
482 .enable = exynos4_clk_ip_peril_ctrl,
483 .ctrlbit = (1 << 15),
487 .enable = exynos4_clk_ip_perir_ctrl,
488 .ctrlbit = (1 << 15),
492 .enable = exynos4_clk_ip_perir_ctrl,
493 .ctrlbit = (1 << 14),
497 .enable = exynos4_clk_ip_fsys_ctrl ,
498 .ctrlbit = (1 << 12),
502 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 13),
507 .enable = exynos4_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 16),
512 .enable = exynos4_clk_ip_peril_ctrl,
513 .ctrlbit = (1 << 17),
517 .enable = exynos4_clk_ip_peril_ctrl,
518 .ctrlbit = (1 << 18),
522 .enable = exynos4_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19),
527 .enable = exynos4_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20),
532 .enable = exynos4_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21),
537 .enable = exynos4_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27),
542 .enable = exynos4_clk_ip_image_ctrl,
547 .parent = &clk_aclk_100.clk,
548 .enable = exynos4_clk_ip_peril_ctrl,
553 .parent = &clk_aclk_100.clk,
554 .enable = exynos4_clk_ip_peril_ctrl,
559 .parent = &clk_aclk_100.clk,
560 .enable = exynos4_clk_ip_peril_ctrl,
565 .parent = &clk_aclk_100.clk,
566 .enable = exynos4_clk_ip_peril_ctrl,
571 .parent = &clk_aclk_100.clk,
572 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 10),
577 .parent = &clk_aclk_100.clk,
578 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 11),
583 .parent = &clk_aclk_100.clk,
584 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 12),
589 .parent = &clk_aclk_100.clk,
590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 13),
595 static struct clk init_clocks[] = {
599 .enable = exynos4_clk_ip_peril_ctrl,
604 .enable = exynos4_clk_ip_peril_ctrl,
609 .enable = exynos4_clk_ip_peril_ctrl,
614 .enable = exynos4_clk_ip_peril_ctrl,
619 .enable = exynos4_clk_ip_peril_ctrl,
624 .enable = exynos4_clk_ip_peril_ctrl,
629 static struct clk *clkset_group_list[] = {
630 [0] = &clk_ext_xtal_mux,
632 [2] = &clk_sclk_hdmi27m,
633 [3] = &clk_sclk_usbphy0,
634 [4] = &clk_sclk_usbphy1,
635 [5] = &clk_sclk_hdmiphy,
636 [6] = &clk_mout_mpll.clk,
637 [7] = &clk_mout_epll.clk,
638 [8] = &clk_sclk_vpll.clk,
641 static struct clksrc_sources clkset_group = {
642 .sources = clkset_group_list,
643 .nr_sources = ARRAY_SIZE(clkset_group_list),
646 static struct clk *clkset_mout_g2d0_list[] = {
647 [0] = &clk_mout_mpll.clk,
648 [1] = &clk_sclk_apll.clk,
651 static struct clksrc_sources clkset_mout_g2d0 = {
652 .sources = clkset_mout_g2d0_list,
653 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
656 static struct clksrc_clk clk_mout_g2d0 = {
661 .sources = &clkset_mout_g2d0,
662 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
665 static struct clk *clkset_mout_g2d1_list[] = {
666 [0] = &clk_mout_epll.clk,
667 [1] = &clk_sclk_vpll.clk,
670 static struct clksrc_sources clkset_mout_g2d1 = {
671 .sources = clkset_mout_g2d1_list,
672 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
675 static struct clksrc_clk clk_mout_g2d1 = {
680 .sources = &clkset_mout_g2d1,
681 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
684 static struct clk *clkset_mout_g2d_list[] = {
685 [0] = &clk_mout_g2d0.clk,
686 [1] = &clk_mout_g2d1.clk,
689 static struct clksrc_sources clkset_mout_g2d = {
690 .sources = clkset_mout_g2d_list,
691 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
694 static struct clksrc_clk clk_dout_mmc0 = {
699 .sources = &clkset_group,
700 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
701 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
704 static struct clksrc_clk clk_dout_mmc1 = {
709 .sources = &clkset_group,
710 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
711 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
714 static struct clksrc_clk clk_dout_mmc2 = {
719 .sources = &clkset_group,
720 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
721 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
724 static struct clksrc_clk clk_dout_mmc3 = {
729 .sources = &clkset_group,
730 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
731 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
734 static struct clksrc_clk clk_dout_mmc4 = {
739 .sources = &clkset_group,
740 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
741 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
744 static struct clksrc_clk clksrcs[] = {
749 .enable = exynos4_clksrc_mask_peril0_ctrl,
752 .sources = &clkset_group,
753 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
754 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
759 .enable = exynos4_clksrc_mask_peril0_ctrl,
762 .sources = &clkset_group,
763 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
764 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
769 .enable = exynos4_clksrc_mask_peril0_ctrl,
772 .sources = &clkset_group,
773 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
774 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
779 .enable = exynos4_clksrc_mask_peril0_ctrl,
780 .ctrlbit = (1 << 12),
782 .sources = &clkset_group,
783 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
784 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
789 .enable = exynos4_clksrc_mask_peril0_ctrl,
790 .ctrlbit = (1 << 24),
792 .sources = &clkset_group,
793 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
794 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
799 .enable = exynos4_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 24),
802 .sources = &clkset_group,
803 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
804 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
809 .enable = exynos4_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 28),
812 .sources = &clkset_group,
813 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
814 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
819 .enable = exynos4_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 16),
822 .sources = &clkset_group,
823 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
824 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
829 .enable = exynos4_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 20),
832 .sources = &clkset_group,
833 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
834 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
839 .enable = exynos4_clksrc_mask_cam_ctrl,
842 .sources = &clkset_group,
843 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
844 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
849 .enable = exynos4_clksrc_mask_cam_ctrl,
852 .sources = &clkset_group,
853 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
854 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
859 .enable = exynos4_clksrc_mask_cam_ctrl,
862 .sources = &clkset_group,
863 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
864 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
869 .enable = exynos4_clksrc_mask_cam_ctrl,
870 .ctrlbit = (1 << 12),
872 .sources = &clkset_group,
873 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
874 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
879 .enable = exynos4_clksrc_mask_lcd0_ctrl,
882 .sources = &clkset_group,
883 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
884 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
889 .enable = exynos4_clksrc_mask_lcd1_ctrl,
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
899 .enable = exynos4_clksrc_mask_fsys_ctrl,
900 .ctrlbit = (1 << 24),
902 .sources = &clkset_mout_corebus,
903 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
904 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
909 .enable = exynos4_clksrc_mask_peril1_ctrl,
910 .ctrlbit = (1 << 16),
912 .sources = &clkset_group,
913 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
914 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
919 .enable = exynos4_clksrc_mask_peril1_ctrl,
920 .ctrlbit = (1 << 20),
922 .sources = &clkset_group,
923 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
924 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
929 .enable = exynos4_clksrc_mask_peril1_ctrl,
930 .ctrlbit = (1 << 24),
932 .sources = &clkset_group,
933 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
934 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
937 .name = "sclk_fimg2d",
940 .sources = &clkset_mout_g2d,
941 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
942 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
947 .parent = &clk_dout_mmc0.clk,
948 .enable = exynos4_clksrc_mask_fsys_ctrl,
951 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
956 .parent = &clk_dout_mmc1.clk,
957 .enable = exynos4_clksrc_mask_fsys_ctrl,
960 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
965 .parent = &clk_dout_mmc2.clk,
966 .enable = exynos4_clksrc_mask_fsys_ctrl,
969 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
974 .parent = &clk_dout_mmc3.clk,
975 .enable = exynos4_clksrc_mask_fsys_ctrl,
976 .ctrlbit = (1 << 12),
978 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
983 .parent = &clk_dout_mmc4.clk,
984 .enable = exynos4_clksrc_mask_fsys_ctrl,
985 .ctrlbit = (1 << 16),
987 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
991 /* Clock initialization code */
992 static struct clksrc_clk *sysclks[] = {
1023 static int xtal_rate;
1025 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1030 static struct clk_ops exynos4_fout_apll_ops = {
1031 .get_rate = exynos4_fout_apll_get_rate,
1034 void __init_or_cpufreq exynos4_setup_clocks(void)
1036 struct clk *xtal_clk;
1041 unsigned long vpllsrc;
1043 unsigned long armclk;
1044 unsigned long sclk_dmc;
1045 unsigned long aclk_200;
1046 unsigned long aclk_100;
1047 unsigned long aclk_160;
1048 unsigned long aclk_133;
1051 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1053 xtal_clk = clk_get(NULL, "xtal");
1054 BUG_ON(IS_ERR(xtal_clk));
1056 xtal = clk_get_rate(xtal_clk);
1062 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1064 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1065 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1066 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1067 __raw_readl(S5P_EPLL_CON1), pll_4600);
1069 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1071 __raw_readl(S5P_VPLL_CON1), pll_4650);
1073 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1074 clk_fout_mpll.rate = mpll;
1075 clk_fout_epll.rate = epll;
1076 clk_fout_vpll.rate = vpll;
1078 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1079 apll, mpll, epll, vpll);
1081 armclk = clk_get_rate(&clk_armclk.clk);
1082 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1084 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1085 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1086 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1087 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1089 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1090 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1091 armclk, sclk_dmc, aclk_200,
1092 aclk_100, aclk_160, aclk_133);
1094 clk_f.rate = armclk;
1095 clk_h.rate = sclk_dmc;
1096 clk_p.rate = aclk_100;
1098 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1099 s3c_set_clksrc(&clksrcs[ptr], true);
1102 static struct clk *clks[] __initdata = {
1103 /* Nothing here yet */
1106 void __init exynos4_register_clocks(void)
1110 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1112 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1113 s3c_register_clksrc(sysclks[ptr], 1);
1115 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1116 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1118 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1119 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));