1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
25 #include <mach/regs-clock.h>
26 #include <mach/sysmmu.h>
28 static struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m",
33 static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
37 static struct clk clk_sclk_usbphy0 = {
38 .name = "sclk_usbphy0",
42 static struct clk clk_sclk_usbphy1 = {
43 .name = "sclk_usbphy1",
46 static struct clk dummy_apb_pclk = {
51 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
53 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
56 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
58 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
61 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
63 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
66 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
68 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
71 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
73 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
76 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
78 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
81 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
83 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
86 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
88 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
91 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
93 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
96 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
98 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
101 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
103 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
106 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
108 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
111 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
113 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
116 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
118 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
121 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
123 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
126 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
128 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
131 /* Core list of CMU_CPU side */
133 static struct clksrc_clk clk_mout_apll = {
137 .sources = &clk_src_apll,
138 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
141 static struct clksrc_clk clk_sclk_apll = {
144 .parent = &clk_mout_apll.clk,
146 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
149 static struct clksrc_clk clk_mout_epll = {
153 .sources = &clk_src_epll,
154 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
157 static struct clksrc_clk clk_mout_mpll = {
161 .sources = &clk_src_mpll,
162 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
165 static struct clk *clkset_moutcore_list[] = {
166 [0] = &clk_mout_apll.clk,
167 [1] = &clk_mout_mpll.clk,
170 static struct clksrc_sources clkset_moutcore = {
171 .sources = clkset_moutcore_list,
172 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
175 static struct clksrc_clk clk_moutcore = {
179 .sources = &clkset_moutcore,
180 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
183 static struct clksrc_clk clk_coreclk = {
186 .parent = &clk_moutcore.clk,
188 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
191 static struct clksrc_clk clk_armclk = {
194 .parent = &clk_coreclk.clk,
198 static struct clksrc_clk clk_aclk_corem0 = {
200 .name = "aclk_corem0",
201 .parent = &clk_coreclk.clk,
203 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
206 static struct clksrc_clk clk_aclk_cores = {
208 .name = "aclk_cores",
209 .parent = &clk_coreclk.clk,
211 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
214 static struct clksrc_clk clk_aclk_corem1 = {
216 .name = "aclk_corem1",
217 .parent = &clk_coreclk.clk,
219 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
222 static struct clksrc_clk clk_periphclk = {
225 .parent = &clk_coreclk.clk,
227 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
230 /* Core list of CMU_CORE side */
232 static struct clk *clkset_corebus_list[] = {
233 [0] = &clk_mout_mpll.clk,
234 [1] = &clk_sclk_apll.clk,
237 static struct clksrc_sources clkset_mout_corebus = {
238 .sources = clkset_corebus_list,
239 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
242 static struct clksrc_clk clk_mout_corebus = {
244 .name = "mout_corebus",
246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
250 static struct clksrc_clk clk_sclk_dmc = {
253 .parent = &clk_mout_corebus.clk,
255 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
258 static struct clksrc_clk clk_aclk_cored = {
260 .name = "aclk_cored",
261 .parent = &clk_sclk_dmc.clk,
263 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
266 static struct clksrc_clk clk_aclk_corep = {
268 .name = "aclk_corep",
269 .parent = &clk_aclk_cored.clk,
271 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
274 static struct clksrc_clk clk_aclk_acp = {
277 .parent = &clk_mout_corebus.clk,
279 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
282 static struct clksrc_clk clk_pclk_acp = {
285 .parent = &clk_aclk_acp.clk,
287 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
290 /* Core list of CMU_TOP side */
292 static struct clk *clkset_aclk_top_list[] = {
293 [0] = &clk_mout_mpll.clk,
294 [1] = &clk_sclk_apll.clk,
297 static struct clksrc_sources clkset_aclk = {
298 .sources = clkset_aclk_top_list,
299 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
302 static struct clksrc_clk clk_aclk_200 = {
306 .sources = &clkset_aclk,
307 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
308 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
311 static struct clksrc_clk clk_aclk_100 = {
315 .sources = &clkset_aclk,
316 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
317 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
320 static struct clksrc_clk clk_aclk_160 = {
324 .sources = &clkset_aclk,
325 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
326 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
329 static struct clksrc_clk clk_aclk_133 = {
333 .sources = &clkset_aclk,
334 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
335 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
338 static struct clk *clkset_vpllsrc_list[] = {
340 [1] = &clk_sclk_hdmi27m,
343 static struct clksrc_sources clkset_vpllsrc = {
344 .sources = clkset_vpllsrc_list,
345 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
348 static struct clksrc_clk clk_vpllsrc = {
351 .enable = exynos4_clksrc_mask_top_ctrl,
354 .sources = &clkset_vpllsrc,
355 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
358 static struct clk *clkset_sclk_vpll_list[] = {
359 [0] = &clk_vpllsrc.clk,
360 [1] = &clk_fout_vpll,
363 static struct clksrc_sources clkset_sclk_vpll = {
364 .sources = clkset_sclk_vpll_list,
365 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
368 static struct clksrc_clk clk_sclk_vpll = {
372 .sources = &clkset_sclk_vpll,
373 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
376 static struct clk init_clocks_off[] = {
379 .parent = &clk_aclk_100.clk,
380 .enable = exynos4_clk_ip_peril_ctrl,
384 .devname = "s5p-mipi-csis.0",
385 .enable = exynos4_clk_ip_cam_ctrl,
389 .devname = "s5p-mipi-csis.1",
390 .enable = exynos4_clk_ip_cam_ctrl,
394 .devname = "exynos4-fimc.0",
395 .enable = exynos4_clk_ip_cam_ctrl,
399 .devname = "exynos4-fimc.1",
400 .enable = exynos4_clk_ip_cam_ctrl,
404 .devname = "exynos4-fimc.2",
405 .enable = exynos4_clk_ip_cam_ctrl,
409 .devname = "exynos4-fimc.3",
410 .enable = exynos4_clk_ip_cam_ctrl,
414 .devname = "exynos4-fb.0",
415 .enable = exynos4_clk_ip_lcd0_ctrl,
419 .devname = "exynos4-fb.1",
420 .enable = exynos4_clk_ip_lcd1_ctrl,
424 .parent = &clk_aclk_133.clk,
425 .enable = exynos4_clk_ip_fsys_ctrl,
429 .devname = "s3c-sdhci.0",
430 .parent = &clk_aclk_133.clk,
431 .enable = exynos4_clk_ip_fsys_ctrl,
435 .devname = "s3c-sdhci.1",
436 .parent = &clk_aclk_133.clk,
437 .enable = exynos4_clk_ip_fsys_ctrl,
441 .devname = "s3c-sdhci.2",
442 .parent = &clk_aclk_133.clk,
443 .enable = exynos4_clk_ip_fsys_ctrl,
447 .devname = "s3c-sdhci.3",
448 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl,
453 .parent = &clk_aclk_133.clk,
454 .enable = exynos4_clk_ip_fsys_ctrl,
458 .parent = &clk_aclk_133.clk,
459 .enable = exynos4_clk_ip_fsys_ctrl,
460 .ctrlbit = (1 << 10),
463 .devname = "dma-pl330.0",
464 .enable = exynos4_clk_ip_fsys_ctrl,
468 .devname = "dma-pl330.1",
469 .enable = exynos4_clk_ip_fsys_ctrl,
473 .enable = exynos4_clk_ip_peril_ctrl,
474 .ctrlbit = (1 << 15),
477 .enable = exynos4_clk_ip_perir_ctrl,
478 .ctrlbit = (1 << 16),
481 .enable = exynos4_clk_ip_perir_ctrl,
482 .ctrlbit = (1 << 15),
485 .parent = &clk_aclk_100.clk,
486 .enable = exynos4_clk_ip_perir_ctrl,
487 .ctrlbit = (1 << 14),
490 .enable = exynos4_clk_ip_fsys_ctrl ,
491 .ctrlbit = (1 << 12),
494 .enable = exynos4_clk_ip_fsys_ctrl,
495 .ctrlbit = (1 << 13),
498 .devname = "s3c64xx-spi.0",
499 .enable = exynos4_clk_ip_peril_ctrl,
500 .ctrlbit = (1 << 16),
503 .devname = "s3c64xx-spi.1",
504 .enable = exynos4_clk_ip_peril_ctrl,
505 .ctrlbit = (1 << 17),
508 .devname = "s3c64xx-spi.2",
509 .enable = exynos4_clk_ip_peril_ctrl,
510 .ctrlbit = (1 << 18),
513 .devname = "samsung-i2s.0",
514 .enable = exynos4_clk_ip_peril_ctrl,
515 .ctrlbit = (1 << 19),
518 .devname = "samsung-i2s.1",
519 .enable = exynos4_clk_ip_peril_ctrl,
520 .ctrlbit = (1 << 20),
523 .devname = "samsung-i2s.2",
524 .enable = exynos4_clk_ip_peril_ctrl,
525 .ctrlbit = (1 << 21),
528 .devname = "samsung-ac97",
529 .enable = exynos4_clk_ip_peril_ctrl,
530 .ctrlbit = (1 << 27),
533 .enable = exynos4_clk_ip_image_ctrl,
537 .devname = "s5p-mfc",
538 .enable = exynos4_clk_ip_mfc_ctrl,
542 .devname = "s3c2440-i2c.0",
543 .parent = &clk_aclk_100.clk,
544 .enable = exynos4_clk_ip_peril_ctrl,
548 .devname = "s3c2440-i2c.1",
549 .parent = &clk_aclk_100.clk,
550 .enable = exynos4_clk_ip_peril_ctrl,
554 .devname = "s3c2440-i2c.2",
555 .parent = &clk_aclk_100.clk,
556 .enable = exynos4_clk_ip_peril_ctrl,
560 .devname = "s3c2440-i2c.3",
561 .parent = &clk_aclk_100.clk,
562 .enable = exynos4_clk_ip_peril_ctrl,
566 .devname = "s3c2440-i2c.4",
567 .parent = &clk_aclk_100.clk,
568 .enable = exynos4_clk_ip_peril_ctrl,
569 .ctrlbit = (1 << 10),
572 .devname = "s3c2440-i2c.5",
573 .parent = &clk_aclk_100.clk,
574 .enable = exynos4_clk_ip_peril_ctrl,
575 .ctrlbit = (1 << 11),
578 .devname = "s3c2440-i2c.6",
579 .parent = &clk_aclk_100.clk,
580 .enable = exynos4_clk_ip_peril_ctrl,
581 .ctrlbit = (1 << 12),
584 .devname = "s3c2440-i2c.7",
585 .parent = &clk_aclk_100.clk,
586 .enable = exynos4_clk_ip_peril_ctrl,
587 .ctrlbit = (1 << 13),
589 .name = "SYSMMU_MDMA",
590 .enable = exynos4_clk_ip_image_ctrl,
593 .name = "SYSMMU_FIMC0",
594 .enable = exynos4_clk_ip_cam_ctrl,
597 .name = "SYSMMU_FIMC1",
598 .enable = exynos4_clk_ip_cam_ctrl,
601 .name = "SYSMMU_FIMC2",
602 .enable = exynos4_clk_ip_cam_ctrl,
605 .name = "SYSMMU_FIMC3",
606 .enable = exynos4_clk_ip_cam_ctrl,
607 .ctrlbit = (1 << 10),
609 .name = "SYSMMU_JPEG",
610 .enable = exynos4_clk_ip_cam_ctrl,
611 .ctrlbit = (1 << 11),
613 .name = "SYSMMU_FIMD0",
614 .enable = exynos4_clk_ip_lcd0_ctrl,
617 .name = "SYSMMU_FIMD1",
618 .enable = exynos4_clk_ip_lcd1_ctrl,
621 .name = "SYSMMU_PCIe",
622 .enable = exynos4_clk_ip_fsys_ctrl,
623 .ctrlbit = (1 << 18),
625 .name = "SYSMMU_G2D",
626 .enable = exynos4_clk_ip_image_ctrl,
629 .name = "SYSMMU_ROTATOR",
630 .enable = exynos4_clk_ip_image_ctrl,
634 .enable = exynos4_clk_ip_tv_ctrl,
637 .name = "SYSMMU_MFC_L",
638 .enable = exynos4_clk_ip_mfc_ctrl,
641 .name = "SYSMMU_MFC_R",
642 .enable = exynos4_clk_ip_mfc_ctrl,
647 static struct clk init_clocks[] = {
650 .devname = "s5pv210-uart.0",
651 .enable = exynos4_clk_ip_peril_ctrl,
655 .devname = "s5pv210-uart.1",
656 .enable = exynos4_clk_ip_peril_ctrl,
660 .devname = "s5pv210-uart.2",
661 .enable = exynos4_clk_ip_peril_ctrl,
665 .devname = "s5pv210-uart.3",
666 .enable = exynos4_clk_ip_peril_ctrl,
670 .devname = "s5pv210-uart.4",
671 .enable = exynos4_clk_ip_peril_ctrl,
675 .devname = "s5pv210-uart.5",
676 .enable = exynos4_clk_ip_peril_ctrl,
681 static struct clk *clkset_group_list[] = {
682 [0] = &clk_ext_xtal_mux,
684 [2] = &clk_sclk_hdmi27m,
685 [3] = &clk_sclk_usbphy0,
686 [4] = &clk_sclk_usbphy1,
687 [5] = &clk_sclk_hdmiphy,
688 [6] = &clk_mout_mpll.clk,
689 [7] = &clk_mout_epll.clk,
690 [8] = &clk_sclk_vpll.clk,
693 static struct clksrc_sources clkset_group = {
694 .sources = clkset_group_list,
695 .nr_sources = ARRAY_SIZE(clkset_group_list),
698 static struct clk *clkset_mout_g2d0_list[] = {
699 [0] = &clk_mout_mpll.clk,
700 [1] = &clk_sclk_apll.clk,
703 static struct clksrc_sources clkset_mout_g2d0 = {
704 .sources = clkset_mout_g2d0_list,
705 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
708 static struct clksrc_clk clk_mout_g2d0 = {
712 .sources = &clkset_mout_g2d0,
713 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
716 static struct clk *clkset_mout_g2d1_list[] = {
717 [0] = &clk_mout_epll.clk,
718 [1] = &clk_sclk_vpll.clk,
721 static struct clksrc_sources clkset_mout_g2d1 = {
722 .sources = clkset_mout_g2d1_list,
723 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
726 static struct clksrc_clk clk_mout_g2d1 = {
730 .sources = &clkset_mout_g2d1,
731 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
734 static struct clk *clkset_mout_g2d_list[] = {
735 [0] = &clk_mout_g2d0.clk,
736 [1] = &clk_mout_g2d1.clk,
739 static struct clksrc_sources clkset_mout_g2d = {
740 .sources = clkset_mout_g2d_list,
741 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
744 static struct clk *clkset_mout_mfc0_list[] = {
745 [0] = &clk_mout_mpll.clk,
746 [1] = &clk_sclk_apll.clk,
749 static struct clksrc_sources clkset_mout_mfc0 = {
750 .sources = clkset_mout_mfc0_list,
751 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
754 static struct clksrc_clk clk_mout_mfc0 = {
758 .sources = &clkset_mout_mfc0,
759 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
762 static struct clk *clkset_mout_mfc1_list[] = {
763 [0] = &clk_mout_epll.clk,
764 [1] = &clk_sclk_vpll.clk,
767 static struct clksrc_sources clkset_mout_mfc1 = {
768 .sources = clkset_mout_mfc1_list,
769 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
772 static struct clksrc_clk clk_mout_mfc1 = {
776 .sources = &clkset_mout_mfc1,
777 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
780 static struct clk *clkset_mout_mfc_list[] = {
781 [0] = &clk_mout_mfc0.clk,
782 [1] = &clk_mout_mfc1.clk,
785 static struct clksrc_sources clkset_mout_mfc = {
786 .sources = clkset_mout_mfc_list,
787 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
790 static struct clksrc_clk clk_dout_mmc0 = {
794 .sources = &clkset_group,
795 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
796 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
799 static struct clksrc_clk clk_dout_mmc1 = {
803 .sources = &clkset_group,
804 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
805 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
808 static struct clksrc_clk clk_dout_mmc2 = {
812 .sources = &clkset_group,
813 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
814 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
817 static struct clksrc_clk clk_dout_mmc3 = {
821 .sources = &clkset_group,
822 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
823 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
826 static struct clksrc_clk clk_dout_mmc4 = {
830 .sources = &clkset_group,
831 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
832 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
835 static struct clksrc_clk clksrcs[] = {
839 .devname = "s5pv210-uart.0",
840 .enable = exynos4_clksrc_mask_peril0_ctrl,
843 .sources = &clkset_group,
844 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
845 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
849 .devname = "s5pv210-uart.1",
850 .enable = exynos4_clksrc_mask_peril0_ctrl,
853 .sources = &clkset_group,
854 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
855 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
859 .devname = "s5pv210-uart.2",
860 .enable = exynos4_clksrc_mask_peril0_ctrl,
863 .sources = &clkset_group,
864 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
865 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
869 .devname = "s5pv210-uart.3",
870 .enable = exynos4_clksrc_mask_peril0_ctrl,
871 .ctrlbit = (1 << 12),
873 .sources = &clkset_group,
874 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
875 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
879 .enable = exynos4_clksrc_mask_peril0_ctrl,
880 .ctrlbit = (1 << 24),
882 .sources = &clkset_group,
883 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
884 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
888 .devname = "s5p-mipi-csis.0",
889 .enable = exynos4_clksrc_mask_cam_ctrl,
890 .ctrlbit = (1 << 24),
892 .sources = &clkset_group,
893 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
894 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
898 .devname = "s5p-mipi-csis.1",
899 .enable = exynos4_clksrc_mask_cam_ctrl,
900 .ctrlbit = (1 << 28),
902 .sources = &clkset_group,
903 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
904 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
908 .enable = exynos4_clksrc_mask_cam_ctrl,
909 .ctrlbit = (1 << 16),
911 .sources = &clkset_group,
912 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
913 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
917 .enable = exynos4_clksrc_mask_cam_ctrl,
918 .ctrlbit = (1 << 20),
920 .sources = &clkset_group,
921 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
922 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
926 .devname = "exynos4-fimc.0",
927 .enable = exynos4_clksrc_mask_cam_ctrl,
930 .sources = &clkset_group,
931 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
932 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
936 .devname = "exynos4-fimc.1",
937 .enable = exynos4_clksrc_mask_cam_ctrl,
940 .sources = &clkset_group,
941 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
942 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
946 .devname = "exynos4-fimc.2",
947 .enable = exynos4_clksrc_mask_cam_ctrl,
950 .sources = &clkset_group,
951 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
952 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
956 .devname = "exynos4-fimc.3",
957 .enable = exynos4_clksrc_mask_cam_ctrl,
958 .ctrlbit = (1 << 12),
960 .sources = &clkset_group,
961 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
962 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
966 .devname = "exynos4-fb.0",
967 .enable = exynos4_clksrc_mask_lcd0_ctrl,
970 .sources = &clkset_group,
971 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
972 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
976 .devname = "exynos4-fb.1",
977 .enable = exynos4_clksrc_mask_lcd1_ctrl,
980 .sources = &clkset_group,
981 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
982 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
986 .enable = exynos4_clksrc_mask_fsys_ctrl,
987 .ctrlbit = (1 << 24),
989 .sources = &clkset_mout_corebus,
990 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
991 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
995 .devname = "s3c64xx-spi.0",
996 .enable = exynos4_clksrc_mask_peril1_ctrl,
997 .ctrlbit = (1 << 16),
999 .sources = &clkset_group,
1000 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1001 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1005 .devname = "s3c64xx-spi.1",
1006 .enable = exynos4_clksrc_mask_peril1_ctrl,
1007 .ctrlbit = (1 << 20),
1009 .sources = &clkset_group,
1010 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1011 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1015 .devname = "s3c64xx-spi.2",
1016 .enable = exynos4_clksrc_mask_peril1_ctrl,
1017 .ctrlbit = (1 << 24),
1019 .sources = &clkset_group,
1020 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1021 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1024 .name = "sclk_fimg2d",
1026 .sources = &clkset_mout_g2d,
1027 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1028 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1032 .devname = "s5p-mfc",
1034 .sources = &clkset_mout_mfc,
1035 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1036 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1040 .devname = "s3c-sdhci.0",
1041 .parent = &clk_dout_mmc0.clk,
1042 .enable = exynos4_clksrc_mask_fsys_ctrl,
1043 .ctrlbit = (1 << 0),
1045 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1049 .devname = "s3c-sdhci.1",
1050 .parent = &clk_dout_mmc1.clk,
1051 .enable = exynos4_clksrc_mask_fsys_ctrl,
1052 .ctrlbit = (1 << 4),
1054 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1058 .devname = "s3c-sdhci.2",
1059 .parent = &clk_dout_mmc2.clk,
1060 .enable = exynos4_clksrc_mask_fsys_ctrl,
1061 .ctrlbit = (1 << 8),
1063 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1067 .devname = "s3c-sdhci.3",
1068 .parent = &clk_dout_mmc3.clk,
1069 .enable = exynos4_clksrc_mask_fsys_ctrl,
1070 .ctrlbit = (1 << 12),
1072 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1075 .name = "sclk_dwmmc",
1076 .parent = &clk_dout_mmc4.clk,
1077 .enable = exynos4_clksrc_mask_fsys_ctrl,
1078 .ctrlbit = (1 << 16),
1080 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1084 /* Clock initialization code */
1085 static struct clksrc_clk *sysclks[] = {
1118 static int xtal_rate;
1120 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1122 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1125 static struct clk_ops exynos4_fout_apll_ops = {
1126 .get_rate = exynos4_fout_apll_get_rate,
1129 void __init_or_cpufreq exynos4_setup_clocks(void)
1131 struct clk *xtal_clk;
1136 unsigned long vpllsrc;
1138 unsigned long armclk;
1139 unsigned long sclk_dmc;
1140 unsigned long aclk_200;
1141 unsigned long aclk_100;
1142 unsigned long aclk_160;
1143 unsigned long aclk_133;
1146 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1148 xtal_clk = clk_get(NULL, "xtal");
1149 BUG_ON(IS_ERR(xtal_clk));
1151 xtal = clk_get_rate(xtal_clk);
1157 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1159 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1160 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1161 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1162 __raw_readl(S5P_EPLL_CON1), pll_4600);
1164 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1165 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1166 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1168 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1169 clk_fout_mpll.rate = mpll;
1170 clk_fout_epll.rate = epll;
1171 clk_fout_vpll.rate = vpll;
1173 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1174 apll, mpll, epll, vpll);
1176 armclk = clk_get_rate(&clk_armclk.clk);
1177 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1179 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1180 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1181 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1182 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1184 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1185 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1186 armclk, sclk_dmc, aclk_200,
1187 aclk_100, aclk_160, aclk_133);
1189 clk_f.rate = armclk;
1190 clk_h.rate = sclk_dmc;
1191 clk_p.rate = aclk_100;
1193 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1194 s3c_set_clksrc(&clksrcs[ptr], true);
1197 static struct clk *clks[] __initdata = {
1198 /* Nothing here yet */
1201 void __init exynos4_register_clocks(void)
1205 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1207 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1208 s3c_register_clksrc(sysclks[ptr], 1);
1210 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1211 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1213 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1214 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1216 s3c24xx_register_clock(&dummy_apb_pclk);