arch/arm/mach-exynos4/clock.c

   1 /* linux/arch/arm/mach-exynos4/clock.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * EXYNOS4 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26
  27 static struct clk clk_sclk_hdmi27m = {
  28         .name           = "sclk_hdmi27m",
  29         .id             = -1,
  30         .rate           = 27000000,
  31 };
  32
  33 static struct clk clk_sclk_hdmiphy = {
  34         .name           = "sclk_hdmiphy",
  35         .id             = -1,
  36 };
  37
  38 static struct clk clk_sclk_usbphy0 = {
  39         .name           = "sclk_usbphy0",
  40         .id             = -1,
  41         .rate           = 27000000,
  42 };
  43
  44 static struct clk clk_sclk_usbphy1 = {
  45         .name           = "sclk_usbphy1",
  46         .id             = -1,
  47 };
  48
  49 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
  50 {
  51         return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
  52 }
  53
  54 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
  55 {
  56         return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
  57 }
  58
  59 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
  60 {
  61         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
  62 }
  63
  64 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
  65 {
  66         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
  67 }
  68
  69 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
  70 {
  71         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
  72 }
  73
  74 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
  75 {
  76         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
  77 }
  78
  79 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
  80 {
  81         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
  82 }
  83
  84 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
  85 {
  86         return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
  87 }
  88
  89 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
  90 {
  91         return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
  92 }
  93
  94 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
  95 {
  96         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
  97 }
  98
  99 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 100 {
 101         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 102 }
 103
 104 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 105 {
 106         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 107 }
 108
 109 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 110 {
 111         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 112 }
 113
 114 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
 117 }
 118
 119 /* Core list of CMU_CPU side */
 120
 121 static struct clksrc_clk clk_mout_apll = {
 122         .clk    = {
 123                 .name           = "mout_apll",
 124                 .id             = -1,
 125         },
 126         .sources        = &clk_src_apll,
 127         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 128 };
 129
 130 static struct clksrc_clk clk_sclk_apll = {
 131         .clk    = {
 132                 .name           = "sclk_apll",
 133                 .id             = -1,
 134                 .parent         = &clk_mout_apll.clk,
 135         },
 136         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 137 };
 138
 139 static struct clksrc_clk clk_mout_epll = {
 140         .clk    = {
 141                 .name           = "mout_epll",
 142                 .id             = -1,
 143         },
 144         .sources        = &clk_src_epll,
 145         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 146 };
 147
 148 static struct clksrc_clk clk_mout_mpll = {
 149         .clk = {
 150                 .name           = "mout_mpll",
 151                 .id             = -1,
 152         },
 153         .sources        = &clk_src_mpll,
 154         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
 155 };
 156
 157 static struct clk *clkset_moutcore_list[] = {
 158         [0] = &clk_mout_apll.clk,
 159         [1] = &clk_mout_mpll.clk,
 160 };
 161
 162 static struct clksrc_sources clkset_moutcore = {
 163         .sources        = clkset_moutcore_list,
 164         .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
 165 };
 166
 167 static struct clksrc_clk clk_moutcore = {
 168         .clk    = {
 169                 .name           = "moutcore",
 170                 .id             = -1,
 171         },
 172         .sources        = &clkset_moutcore,
 173         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
 174 };
 175
 176 static struct clksrc_clk clk_coreclk = {
 177         .clk    = {
 178                 .name           = "core_clk",
 179                 .id             = -1,
 180                 .parent         = &clk_moutcore.clk,
 181         },
 182         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
 183 };
 184
 185 static struct clksrc_clk clk_armclk = {
 186         .clk    = {
 187                 .name           = "armclk",
 188                 .id             = -1,
 189                 .parent         = &clk_coreclk.clk,
 190         },
 191 };
 192
 193 static struct clksrc_clk clk_aclk_corem0 = {
 194         .clk    = {
 195                 .name           = "aclk_corem0",
 196                 .id             = -1,
 197                 .parent         = &clk_coreclk.clk,
 198         },
 199         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 200 };
 201
 202 static struct clksrc_clk clk_aclk_cores = {
 203         .clk    = {
 204                 .name           = "aclk_cores",
 205                 .id             = -1,
 206                 .parent         = &clk_coreclk.clk,
 207         },
 208         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
 209 };
 210
 211 static struct clksrc_clk clk_aclk_corem1 = {
 212         .clk    = {
 213                 .name           = "aclk_corem1",
 214                 .id             = -1,
 215                 .parent         = &clk_coreclk.clk,
 216         },
 217         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
 218 };
 219
 220 static struct clksrc_clk clk_periphclk = {
 221         .clk    = {
 222                 .name           = "periphclk",
 223                 .id             = -1,
 224                 .parent         = &clk_coreclk.clk,
 225         },
 226         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 227 };
 228
 229 /* Core list of CMU_CORE side */
 230
 231 static struct clk *clkset_corebus_list[] = {
 232         [0] = &clk_mout_mpll.clk,
 233         [1] = &clk_sclk_apll.clk,
 234 };
 235
 236 static struct clksrc_sources clkset_mout_corebus = {
 237         .sources        = clkset_corebus_list,
 238         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 239 };
 240
 241 static struct clksrc_clk clk_mout_corebus = {
 242         .clk    = {
 243                 .name           = "mout_corebus",
 244                 .id             = -1,
 245         },
 246         .sources        = &clkset_mout_corebus,
 247         .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
 248 };
 249
 250 static struct clksrc_clk clk_sclk_dmc = {
 251         .clk    = {
 252                 .name           = "sclk_dmc",
 253                 .id             = -1,
 254                 .parent         = &clk_mout_corebus.clk,
 255         },
 256         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
 257 };
 258
 259 static struct clksrc_clk clk_aclk_cored = {
 260         .clk    = {
 261                 .name           = "aclk_cored",
 262                 .id             = -1,
 263                 .parent         = &clk_sclk_dmc.clk,
 264         },
 265         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
 266 };
 267
 268 static struct clksrc_clk clk_aclk_corep = {
 269         .clk    = {
 270                 .name           = "aclk_corep",
 271                 .id             = -1,
 272                 .parent         = &clk_aclk_cored.clk,
 273         },
 274         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
 275 };
 276
 277 static struct clksrc_clk clk_aclk_acp = {
 278         .clk    = {
 279                 .name           = "aclk_acp",
 280                 .id             = -1,
 281                 .parent         = &clk_mout_corebus.clk,
 282         },
 283         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
 284 };
 285
 286 static struct clksrc_clk clk_pclk_acp = {
 287         .clk    = {
 288                 .name           = "pclk_acp",
 289                 .id             = -1,
 290                 .parent         = &clk_aclk_acp.clk,
 291         },
 292         .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
 293 };
 294
 295 /* Core list of CMU_TOP side */
 296
 297 static struct clk *clkset_aclk_top_list[] = {
 298         [0] = &clk_mout_mpll.clk,
 299         [1] = &clk_sclk_apll.clk,
 300 };
 301
 302 static struct clksrc_sources clkset_aclk = {
 303         .sources        = clkset_aclk_top_list,
 304         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 305 };
 306
 307 static struct clksrc_clk clk_aclk_200 = {
 308         .clk    = {
 309                 .name           = "aclk_200",
 310                 .id             = -1,
 311         },
 312         .sources        = &clkset_aclk,
 313         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
 314         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 315 };
 316
 317 static struct clksrc_clk clk_aclk_100 = {
 318         .clk    = {
 319                 .name           = "aclk_100",
 320                 .id             = -1,
 321         },
 322         .sources        = &clkset_aclk,
 323         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
 324         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 325 };
 326
 327 static struct clksrc_clk clk_aclk_160 = {
 328         .clk    = {
 329                 .name           = "aclk_160",
 330                 .id             = -1,
 331         },
 332         .sources        = &clkset_aclk,
 333         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
 334         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 335 };
 336
 337 static struct clksrc_clk clk_aclk_133 = {
 338         .clk    = {
 339                 .name           = "aclk_133",
 340                 .id             = -1,
 341         },
 342         .sources        = &clkset_aclk,
 343         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
 344         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 345 };
 346
 347 static struct clk *clkset_vpllsrc_list[] = {
 348         [0] = &clk_fin_vpll,
 349         [1] = &clk_sclk_hdmi27m,
 350 };
 351
 352 static struct clksrc_sources clkset_vpllsrc = {
 353         .sources        = clkset_vpllsrc_list,
 354         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 355 };
 356
 357 static struct clksrc_clk clk_vpllsrc = {
 358         .clk    = {
 359                 .name           = "vpll_src",
 360                 .id             = -1,
 361                 .enable         = exynos4_clksrc_mask_top_ctrl,
 362                 .ctrlbit        = (1 << 0),
 363         },
 364         .sources        = &clkset_vpllsrc,
 365         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
 366 };
 367
 368 static struct clk *clkset_sclk_vpll_list[] = {
 369         [0] = &clk_vpllsrc.clk,
 370         [1] = &clk_fout_vpll,
 371 };
 372
 373 static struct clksrc_sources clkset_sclk_vpll = {
 374         .sources        = clkset_sclk_vpll_list,
 375         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 376 };
 377
 378 static struct clksrc_clk clk_sclk_vpll = {
 379         .clk    = {
 380                 .name           = "sclk_vpll",
 381                 .id             = -1,
 382         },
 383         .sources        = &clkset_sclk_vpll,
 384         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 385 };
 386
 387 static struct clk init_clocks_off[] = {
 388         {
 389                 .name           = "timers",
 390                 .id             = -1,
 391                 .parent         = &clk_aclk_100.clk,
 392                 .enable         = exynos4_clk_ip_peril_ctrl,
 393                 .ctrlbit        = (1<<24),
 394         }, {
 395                 .name           = "csis",
 396                 .id             = 0,
 397                 .enable         = exynos4_clk_ip_cam_ctrl,
 398                 .ctrlbit        = (1 << 4),
 399         }, {
 400                 .name           = "csis",
 401                 .id             = 1,
 402                 .enable         = exynos4_clk_ip_cam_ctrl,
 403                 .ctrlbit        = (1 << 5),
 404         }, {
 405                 .name           = "fimc",
 406                 .id             = 0,
 407                 .enable         = exynos4_clk_ip_cam_ctrl,
 408                 .ctrlbit        = (1 << 0),
 409         }, {
 410                 .name           = "fimc",
 411                 .id             = 1,
 412                 .enable         = exynos4_clk_ip_cam_ctrl,
 413                 .ctrlbit        = (1 << 1),
 414         }, {
 415                 .name           = "fimc",
 416                 .id             = 2,
 417                 .enable         = exynos4_clk_ip_cam_ctrl,
 418                 .ctrlbit        = (1 << 2),
 419         }, {
 420                 .name           = "fimc",
 421                 .id             = 3,
 422                 .enable         = exynos4_clk_ip_cam_ctrl,
 423                 .ctrlbit        = (1 << 3),
 424         }, {
 425                 .name           = "fimd",
 426                 .id             = 0,
 427                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 428                 .ctrlbit        = (1 << 0),
 429         }, {
 430                 .name           = "fimd",
 431                 .id             = 1,
 432                 .enable         = exynos4_clk_ip_lcd1_ctrl,
 433                 .ctrlbit        = (1 << 0),
 434         }, {
 435                 .name           = "hsmmc",
 436                 .id             = 0,
 437                 .parent         = &clk_aclk_133.clk,
 438                 .enable         = exynos4_clk_ip_fsys_ctrl,
 439                 .ctrlbit        = (1 << 5),
 440         }, {
 441                 .name           = "hsmmc",
 442                 .id             = 1,
 443                 .parent         = &clk_aclk_133.clk,
 444                 .enable         = exynos4_clk_ip_fsys_ctrl,
 445                 .ctrlbit        = (1 << 6),
 446         }, {
 447                 .name           = "hsmmc",
 448                 .id             = 2,
 449                 .parent         = &clk_aclk_133.clk,
 450                 .enable         = exynos4_clk_ip_fsys_ctrl,
 451                 .ctrlbit        = (1 << 7),
 452         }, {
 453                 .name           = "hsmmc",
 454                 .id             = 3,
 455                 .parent         = &clk_aclk_133.clk,
 456                 .enable         = exynos4_clk_ip_fsys_ctrl,
 457                 .ctrlbit        = (1 << 8),
 458         }, {
 459                 .name           = "hsmmc",
 460                 .id             = 4,
 461                 .parent         = &clk_aclk_133.clk,
 462                 .enable         = exynos4_clk_ip_fsys_ctrl,
 463                 .ctrlbit        = (1 << 9),
 464         }, {
 465                 .name           = "sata",
 466                 .id             = -1,
 467                 .enable         = exynos4_clk_ip_fsys_ctrl,
 468                 .ctrlbit        = (1 << 10),
 469         }, {
 470                 .name           = "pdma",
 471                 .id             = 0,
 472                 .enable         = exynos4_clk_ip_fsys_ctrl,
 473                 .ctrlbit        = (1 << 0),
 474         }, {
 475                 .name           = "pdma",
 476                 .id             = 1,
 477                 .enable         = exynos4_clk_ip_fsys_ctrl,
 478                 .ctrlbit        = (1 << 1),
 479         }, {
 480                 .name           = "adc",
 481                 .id             = -1,
 482                 .enable         = exynos4_clk_ip_peril_ctrl,
 483                 .ctrlbit        = (1 << 15),
 484         }, {
 485                 .name           = "rtc",
 486                 .id             = -1,
 487                 .enable         = exynos4_clk_ip_perir_ctrl,
 488                 .ctrlbit        = (1 << 15),
 489         }, {
 490                 .name           = "watchdog",
 491                 .id             = -1,
 492                 .parent         = &clk_aclk_100.clk,
 493                 .enable         = exynos4_clk_ip_perir_ctrl,
 494                 .ctrlbit        = (1 << 14),
 495         }, {
 496                 .name           = "usbhost",
 497                 .id             = -1,
 498                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 499                 .ctrlbit        = (1 << 12),
 500         }, {
 501                 .name           = "otg",
 502                 .id             = -1,
 503                 .enable         = exynos4_clk_ip_fsys_ctrl,
 504                 .ctrlbit        = (1 << 13),
 505         }, {
 506                 .name           = "spi",
 507                 .id             = 0,
 508                 .enable         = exynos4_clk_ip_peril_ctrl,
 509                 .ctrlbit        = (1 << 16),
 510         }, {
 511                 .name           = "spi",
 512                 .id             = 1,
 513                 .enable         = exynos4_clk_ip_peril_ctrl,
 514                 .ctrlbit        = (1 << 17),
 515         }, {
 516                 .name           = "spi",
 517                 .id             = 2,
 518                 .enable         = exynos4_clk_ip_peril_ctrl,
 519                 .ctrlbit        = (1 << 18),
 520         }, {
 521                 .name           = "iis",
 522                 .id             = 0,
 523                 .enable         = exynos4_clk_ip_peril_ctrl,
 524                 .ctrlbit        = (1 << 19),
 525         }, {
 526                 .name           = "iis",
 527                 .id             = 1,
 528                 .enable         = exynos4_clk_ip_peril_ctrl,
 529                 .ctrlbit        = (1 << 20),
 530         }, {
 531                 .name           = "iis",
 532                 .id             = 2,
 533                 .enable         = exynos4_clk_ip_peril_ctrl,
 534                 .ctrlbit        = (1 << 21),
 535         }, {
 536                 .name           = "ac97",
 537                 .id             = -1,
 538                 .enable         = exynos4_clk_ip_peril_ctrl,
 539                 .ctrlbit        = (1 << 27),
 540         }, {
 541                 .name           = "fimg2d",
 542                 .id             = -1,
 543                 .enable         = exynos4_clk_ip_image_ctrl,
 544                 .ctrlbit        = (1 << 0),
 545         }, {
 546                 .name           = "i2c",
 547                 .id             = 0,
 548                 .parent         = &clk_aclk_100.clk,
 549                 .enable         = exynos4_clk_ip_peril_ctrl,
 550                 .ctrlbit        = (1 << 6),
 551         }, {
 552                 .name           = "i2c",
 553                 .id             = 1,
 554                 .parent         = &clk_aclk_100.clk,
 555                 .enable         = exynos4_clk_ip_peril_ctrl,
 556                 .ctrlbit        = (1 << 7),
 557         }, {
 558                 .name           = "i2c",
 559                 .id             = 2,
 560                 .parent         = &clk_aclk_100.clk,
 561                 .enable         = exynos4_clk_ip_peril_ctrl,
 562                 .ctrlbit        = (1 << 8),
 563         }, {
 564                 .name           = "i2c",
 565                 .id             = 3,
 566                 .parent         = &clk_aclk_100.clk,
 567                 .enable         = exynos4_clk_ip_peril_ctrl,
 568                 .ctrlbit        = (1 << 9),
 569         }, {
 570                 .name           = "i2c",
 571                 .id             = 4,
 572                 .parent         = &clk_aclk_100.clk,
 573                 .enable         = exynos4_clk_ip_peril_ctrl,
 574                 .ctrlbit        = (1 << 10),
 575         }, {
 576                 .name           = "i2c",
 577                 .id             = 5,
 578                 .parent         = &clk_aclk_100.clk,
 579                 .enable         = exynos4_clk_ip_peril_ctrl,
 580                 .ctrlbit        = (1 << 11),
 581         }, {
 582                 .name           = "i2c",
 583                 .id             = 6,
 584                 .parent         = &clk_aclk_100.clk,
 585                 .enable         = exynos4_clk_ip_peril_ctrl,
 586                 .ctrlbit        = (1 << 12),
 587         }, {
 588                 .name           = "i2c",
 589                 .id             = 7,
 590                 .parent         = &clk_aclk_100.clk,
 591                 .enable         = exynos4_clk_ip_peril_ctrl,
 592                 .ctrlbit        = (1 << 13),
 593         },
 594 };
 595
 596 static struct clk init_clocks[] = {
 597         {
 598                 .name           = "uart",
 599                 .id             = 0,
 600                 .enable         = exynos4_clk_ip_peril_ctrl,
 601                 .ctrlbit        = (1 << 0),
 602         }, {
 603                 .name           = "uart",
 604                 .id             = 1,
 605                 .enable         = exynos4_clk_ip_peril_ctrl,
 606                 .ctrlbit        = (1 << 1),
 607         }, {
 608                 .name           = "uart",
 609                 .id             = 2,
 610                 .enable         = exynos4_clk_ip_peril_ctrl,
 611                 .ctrlbit        = (1 << 2),
 612         }, {
 613                 .name           = "uart",
 614                 .id             = 3,
 615                 .enable         = exynos4_clk_ip_peril_ctrl,
 616                 .ctrlbit        = (1 << 3),
 617         }, {
 618                 .name           = "uart",
 619                 .id             = 4,
 620                 .enable         = exynos4_clk_ip_peril_ctrl,
 621                 .ctrlbit        = (1 << 4),
 622         }, {
 623                 .name           = "uart",
 624                 .id             = 5,
 625                 .enable         = exynos4_clk_ip_peril_ctrl,
 626                 .ctrlbit        = (1 << 5),
 627         }
 628 };
 629
 630 static struct clk *clkset_group_list[] = {
 631         [0] = &clk_ext_xtal_mux,
 632         [1] = &clk_xusbxti,
 633         [2] = &clk_sclk_hdmi27m,
 634         [3] = &clk_sclk_usbphy0,
 635         [4] = &clk_sclk_usbphy1,
 636         [5] = &clk_sclk_hdmiphy,
 637         [6] = &clk_mout_mpll.clk,
 638         [7] = &clk_mout_epll.clk,
 639         [8] = &clk_sclk_vpll.clk,
 640 };
 641
 642 static struct clksrc_sources clkset_group = {
 643         .sources        = clkset_group_list,
 644         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 645 };
 646
 647 static struct clk *clkset_mout_g2d0_list[] = {
 648         [0] = &clk_mout_mpll.clk,
 649         [1] = &clk_sclk_apll.clk,
 650 };
 651
 652 static struct clksrc_sources clkset_mout_g2d0 = {
 653         .sources        = clkset_mout_g2d0_list,
 654         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
 655 };
 656
 657 static struct clksrc_clk clk_mout_g2d0 = {
 658         .clk    = {
 659                 .name           = "mout_g2d0",
 660                 .id             = -1,
 661         },
 662         .sources        = &clkset_mout_g2d0,
 663         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 664 };
 665
 666 static struct clk *clkset_mout_g2d1_list[] = {
 667         [0] = &clk_mout_epll.clk,
 668         [1] = &clk_sclk_vpll.clk,
 669 };
 670
 671 static struct clksrc_sources clkset_mout_g2d1 = {
 672         .sources        = clkset_mout_g2d1_list,
 673         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
 674 };
 675
 676 static struct clksrc_clk clk_mout_g2d1 = {
 677         .clk    = {
 678                 .name           = "mout_g2d1",
 679                 .id             = -1,
 680         },
 681         .sources        = &clkset_mout_g2d1,
 682         .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 683 };
 684
 685 static struct clk *clkset_mout_g2d_list[] = {
 686         [0] = &clk_mout_g2d0.clk,
 687         [1] = &clk_mout_g2d1.clk,
 688 };
 689
 690 static struct clksrc_sources clkset_mout_g2d = {
 691         .sources        = clkset_mout_g2d_list,
 692         .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
 693 };
 694
 695 static struct clksrc_clk clk_dout_mmc0 = {
 696         .clk            = {
 697                 .name           = "dout_mmc0",
 698                 .id             = -1,
 699         },
 700         .sources = &clkset_group,
 701         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
 702         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 703 };
 704
 705 static struct clksrc_clk clk_dout_mmc1 = {
 706         .clk            = {
 707                 .name           = "dout_mmc1",
 708                 .id             = -1,
 709         },
 710         .sources = &clkset_group,
 711         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
 712         .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 713 };
 714
 715 static struct clksrc_clk clk_dout_mmc2 = {
 716         .clk            = {
 717                 .name           = "dout_mmc2",
 718                 .id             = -1,
 719         },
 720         .sources = &clkset_group,
 721         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
 722         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
 723 };
 724
 725 static struct clksrc_clk clk_dout_mmc3 = {
 726         .clk            = {
 727                 .name           = "dout_mmc3",
 728                 .id             = -1,
 729         },
 730         .sources = &clkset_group,
 731         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
 732         .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
 733 };
 734
 735 static struct clksrc_clk clk_dout_mmc4 = {
 736         .clk            = {
 737                 .name           = "dout_mmc4",
 738                 .id             = -1,
 739         },
 740         .sources = &clkset_group,
 741         .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
 742         .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
 743 };
 744
 745 static struct clksrc_clk clksrcs[] = {
 746         {
 747                 .clk    = {
 748                         .name           = "uclk1",
 749                         .id             = 0,
 750                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 751                         .ctrlbit        = (1 << 0),
 752                 },
 753                 .sources = &clkset_group,
 754                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
 755                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
 756         }, {
 757                 .clk            = {
 758                         .name           = "uclk1",
 759                         .id             = 1,
 760                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 761                         .ctrlbit        = (1 << 4),
 762                 },
 763                 .sources = &clkset_group,
 764                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
 765                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
 766         }, {
 767                 .clk            = {
 768                         .name           = "uclk1",
 769                         .id             = 2,
 770                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 771                         .ctrlbit        = (1 << 8),
 772                 },
 773                 .sources = &clkset_group,
 774                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
 775                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
 776         }, {
 777                 .clk            = {
 778                         .name           = "uclk1",
 779                         .id             = 3,
 780                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 781                         .ctrlbit        = (1 << 12),
 782                 },
 783                 .sources = &clkset_group,
 784                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
 785                 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
 786         }, {
 787                 .clk            = {
 788                         .name           = "sclk_pwm",
 789                         .id             = -1,
 790                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
 791                         .ctrlbit        = (1 << 24),
 792                 },
 793                 .sources = &clkset_group,
 794                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
 795                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
 796         }, {
 797                 .clk            = {
 798                         .name           = "sclk_csis",
 799                         .id             = 0,
 800                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 801                         .ctrlbit        = (1 << 24),
 802                 },
 803                 .sources = &clkset_group,
 804                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
 805                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
 806         }, {
 807                 .clk            = {
 808                         .name           = "sclk_csis",
 809                         .id             = 1,
 810                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 811                         .ctrlbit        = (1 << 28),
 812                 },
 813                 .sources = &clkset_group,
 814                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
 815                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
 816         }, {
 817                 .clk            = {
 818                         .name           = "sclk_cam",
 819                         .id             = 0,
 820                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 821                         .ctrlbit        = (1 << 16),
 822                 },
 823                 .sources = &clkset_group,
 824                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
 825                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
 826         }, {
 827                 .clk            = {
 828                         .name           = "sclk_cam",
 829                         .id             = 1,
 830                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 831                         .ctrlbit        = (1 << 20),
 832                 },
 833                 .sources = &clkset_group,
 834                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
 835                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
 836         }, {
 837                 .clk            = {
 838                         .name           = "sclk_fimc",
 839                         .id             = 0,
 840                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 841                         .ctrlbit        = (1 << 0),
 842                 },
 843                 .sources = &clkset_group,
 844                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
 845                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
 846         }, {
 847                 .clk            = {
 848                         .name           = "sclk_fimc",
 849                         .id             = 1,
 850                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 851                         .ctrlbit        = (1 << 4),
 852                 },
 853                 .sources = &clkset_group,
 854                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
 855                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
 856         }, {
 857                 .clk            = {
 858                         .name           = "sclk_fimc",
 859                         .id             = 2,
 860                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 861                         .ctrlbit        = (1 << 8),
 862                 },
 863                 .sources = &clkset_group,
 864                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
 865                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
 866         }, {
 867                 .clk            = {
 868                         .name           = "sclk_fimc",
 869                         .id             = 3,
 870                         .enable         = exynos4_clksrc_mask_cam_ctrl,
 871                         .ctrlbit        = (1 << 12),
 872                 },
 873                 .sources = &clkset_group,
 874                 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
 875                 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
 876         }, {
 877                 .clk            = {
 878                         .name           = "sclk_fimd",
 879                         .id             = 0,
 880                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
 881                         .ctrlbit        = (1 << 0),
 882                 },
 883                 .sources = &clkset_group,
 884                 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
 885                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
 886         }, {
 887                 .clk            = {
 888                         .name           = "sclk_fimd",
 889                         .id             = 1,
 890                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
 891                         .ctrlbit        = (1 << 0),
 892                 },
 893                 .sources = &clkset_group,
 894                 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
 895                 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
 896         }, {
 897                 .clk            = {
 898                         .name           = "sclk_sata",
 899                         .id             = -1,
 900                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 901                         .ctrlbit        = (1 << 24),
 902                 },
 903                 .sources = &clkset_mout_corebus,
 904                 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
 905                 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
 906         }, {
 907                 .clk            = {
 908                         .name           = "sclk_spi",
 909                         .id             = 0,
 910                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 911                         .ctrlbit        = (1 << 16),
 912                 },
 913                 .sources = &clkset_group,
 914                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
 915                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
 916         }, {
 917                 .clk            = {
 918                         .name           = "sclk_spi",
 919                         .id             = 1,
 920                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 921                         .ctrlbit        = (1 << 20),
 922                 },
 923                 .sources = &clkset_group,
 924                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
 925                 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
 926         }, {
 927                 .clk            = {
 928                         .name           = "sclk_spi",
 929                         .id             = 2,
 930                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
 931                         .ctrlbit        = (1 << 24),
 932                 },
 933                 .sources = &clkset_group,
 934                 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
 935                 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
 936         }, {
 937                 .clk            = {
 938                         .name           = "sclk_fimg2d",
 939                         .id             = -1,
 940                 },
 941                 .sources = &clkset_mout_g2d,
 942                 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
 943                 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
 944         }, {
 945                 .clk            = {
 946                         .name           = "sclk_mmc",
 947                         .id             = 0,
 948                         .parent         = &clk_dout_mmc0.clk,
 949                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 950                         .ctrlbit        = (1 << 0),
 951                 },
 952                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
 953         }, {
 954                 .clk            = {
 955                         .name           = "sclk_mmc",
 956                         .id             = 1,
 957                         .parent         = &clk_dout_mmc1.clk,
 958                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 959                         .ctrlbit        = (1 << 4),
 960                 },
 961                 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
 962         }, {
 963                 .clk            = {
 964                         .name           = "sclk_mmc",
 965                         .id             = 2,
 966                         .parent         = &clk_dout_mmc2.clk,
 967                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 968                         .ctrlbit        = (1 << 8),
 969                 },
 970                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
 971         }, {
 972                 .clk            = {
 973                         .name           = "sclk_mmc",
 974                         .id             = 3,
 975                         .parent         = &clk_dout_mmc3.clk,
 976                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 977                         .ctrlbit        = (1 << 12),
 978                 },
 979                 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 980         }, {
 981                 .clk            = {
 982                         .name           = "sclk_mmc",
 983                         .id             = 4,
 984                         .parent         = &clk_dout_mmc4.clk,
 985                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
 986                         .ctrlbit        = (1 << 16),
 987                 },
 988                 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
 989         }
 990 };
 991
 992 /* Clock initialization code */
 993 static struct clksrc_clk *sysclks[] = {
 994         &clk_mout_apll,
 995         &clk_sclk_apll,
 996         &clk_mout_epll,
 997         &clk_mout_mpll,
 998         &clk_moutcore,
 999         &clk_coreclk,
1000         &clk_armclk,
1001         &clk_aclk_corem0,
1002         &clk_aclk_cores,
1003         &clk_aclk_corem1,
1004         &clk_periphclk,
1005         &clk_mout_corebus,
1006         &clk_sclk_dmc,
1007         &clk_aclk_cored,
1008         &clk_aclk_corep,
1009         &clk_aclk_acp,
1010         &clk_pclk_acp,
1011         &clk_vpllsrc,
1012         &clk_sclk_vpll,
1013         &clk_aclk_200,
1014         &clk_aclk_100,
1015         &clk_aclk_160,
1016         &clk_aclk_133,
1017         &clk_dout_mmc0,
1018         &clk_dout_mmc1,
1019         &clk_dout_mmc2,
1020         &clk_dout_mmc3,
1021         &clk_dout_mmc4,
1022 };
1023
1024 static int xtal_rate;
1025
1026 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1027 {
1028         return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1029 }
1030
1031 static struct clk_ops exynos4_fout_apll_ops = {
1032         .get_rate = exynos4_fout_apll_get_rate,
1033 };
1034
1035 void __init_or_cpufreq exynos4_setup_clocks(void)
1036 {
1037         struct clk *xtal_clk;
1038         unsigned long apll;
1039         unsigned long mpll;
1040         unsigned long epll;
1041         unsigned long vpll;
1042         unsigned long vpllsrc;
1043         unsigned long xtal;
1044         unsigned long armclk;
1045         unsigned long sclk_dmc;
1046         unsigned long aclk_200;
1047         unsigned long aclk_100;
1048         unsigned long aclk_160;
1049         unsigned long aclk_133;
1050         unsigned int ptr;
1051
1052         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1053
1054         xtal_clk = clk_get(NULL, "xtal");
1055         BUG_ON(IS_ERR(xtal_clk));
1056
1057         xtal = clk_get_rate(xtal_clk);
1058
1059         xtal_rate = xtal;
1060
1061         clk_put(xtal_clk);
1062
1063         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1064
1065         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1066         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1067         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1068                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1069
1070         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1071         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1072                                 __raw_readl(S5P_VPLL_CON1), pll_4650);
1073
1074         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1075         clk_fout_mpll.rate = mpll;
1076         clk_fout_epll.rate = epll;
1077         clk_fout_vpll.rate = vpll;
1078
1079         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1080                         apll, mpll, epll, vpll);
1081
1082         armclk = clk_get_rate(&clk_armclk.clk);
1083         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1084
1085         aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1086         aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1087         aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1088         aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1089
1090         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1091                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1092                         armclk, sclk_dmc, aclk_200,
1093                         aclk_100, aclk_160, aclk_133);
1094
1095         clk_f.rate = armclk;
1096         clk_h.rate = sclk_dmc;
1097         clk_p.rate = aclk_100;
1098
1099         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1100                 s3c_set_clksrc(&clksrcs[ptr], true);
1101 }
1102
1103 static struct clk *clks[] __initdata = {
1104         /* Nothing here yet */
1105 };
1106
1107 void __init exynos4_register_clocks(void)
1108 {
1109         int ptr;
1110
1111         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1112
1113         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1114                 s3c_register_clksrc(sysclks[ptr], 1);
1115
1116         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1117         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1118
1119         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1120         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1121
1122         s3c_pwmclk_init();
1123 }