1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
25 #include <mach/regs-clock.h>
27 static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m",
33 static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
38 static struct clk clk_sclk_usbphy0 = {
39 .name = "sclk_usbphy0",
44 static struct clk clk_sclk_usbphy1 = {
45 .name = "sclk_usbphy1",
49 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
54 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
59 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
64 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
69 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
74 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
79 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
84 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
89 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
94 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
99 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
104 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
109 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
114 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
119 /* Core list of CMU_CPU side */
121 static struct clksrc_clk clk_mout_apll = {
126 .sources = &clk_src_apll,
127 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
130 static struct clksrc_clk clk_sclk_apll = {
134 .parent = &clk_mout_apll.clk,
136 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
139 static struct clksrc_clk clk_mout_epll = {
144 .sources = &clk_src_epll,
145 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
148 static struct clksrc_clk clk_mout_mpll = {
153 .sources = &clk_src_mpll,
154 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
157 static struct clk *clkset_moutcore_list[] = {
158 [0] = &clk_mout_apll.clk,
159 [1] = &clk_mout_mpll.clk,
162 static struct clksrc_sources clkset_moutcore = {
163 .sources = clkset_moutcore_list,
164 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
167 static struct clksrc_clk clk_moutcore = {
172 .sources = &clkset_moutcore,
173 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
176 static struct clksrc_clk clk_coreclk = {
180 .parent = &clk_moutcore.clk,
182 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
185 static struct clksrc_clk clk_armclk = {
189 .parent = &clk_coreclk.clk,
193 static struct clksrc_clk clk_aclk_corem0 = {
195 .name = "aclk_corem0",
197 .parent = &clk_coreclk.clk,
199 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
202 static struct clksrc_clk clk_aclk_cores = {
204 .name = "aclk_cores",
206 .parent = &clk_coreclk.clk,
208 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
211 static struct clksrc_clk clk_aclk_corem1 = {
213 .name = "aclk_corem1",
215 .parent = &clk_coreclk.clk,
217 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
220 static struct clksrc_clk clk_periphclk = {
224 .parent = &clk_coreclk.clk,
226 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
229 /* Core list of CMU_CORE side */
231 static struct clk *clkset_corebus_list[] = {
232 [0] = &clk_mout_mpll.clk,
233 [1] = &clk_sclk_apll.clk,
236 static struct clksrc_sources clkset_mout_corebus = {
237 .sources = clkset_corebus_list,
238 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
241 static struct clksrc_clk clk_mout_corebus = {
243 .name = "mout_corebus",
246 .sources = &clkset_mout_corebus,
247 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
250 static struct clksrc_clk clk_sclk_dmc = {
254 .parent = &clk_mout_corebus.clk,
256 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
259 static struct clksrc_clk clk_aclk_cored = {
261 .name = "aclk_cored",
263 .parent = &clk_sclk_dmc.clk,
265 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
268 static struct clksrc_clk clk_aclk_corep = {
270 .name = "aclk_corep",
272 .parent = &clk_aclk_cored.clk,
274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
277 static struct clksrc_clk clk_aclk_acp = {
281 .parent = &clk_mout_corebus.clk,
283 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
286 static struct clksrc_clk clk_pclk_acp = {
290 .parent = &clk_aclk_acp.clk,
292 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
295 /* Core list of CMU_TOP side */
297 static struct clk *clkset_aclk_top_list[] = {
298 [0] = &clk_mout_mpll.clk,
299 [1] = &clk_sclk_apll.clk,
302 static struct clksrc_sources clkset_aclk = {
303 .sources = clkset_aclk_top_list,
304 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
307 static struct clksrc_clk clk_aclk_200 = {
312 .sources = &clkset_aclk,
313 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
314 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
317 static struct clksrc_clk clk_aclk_100 = {
322 .sources = &clkset_aclk,
323 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
324 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
327 static struct clksrc_clk clk_aclk_160 = {
332 .sources = &clkset_aclk,
333 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
334 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
337 static struct clksrc_clk clk_aclk_133 = {
342 .sources = &clkset_aclk,
343 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
344 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
347 static struct clk *clkset_vpllsrc_list[] = {
349 [1] = &clk_sclk_hdmi27m,
352 static struct clksrc_sources clkset_vpllsrc = {
353 .sources = clkset_vpllsrc_list,
354 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
357 static struct clksrc_clk clk_vpllsrc = {
361 .enable = exynos4_clksrc_mask_top_ctrl,
364 .sources = &clkset_vpllsrc,
365 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
368 static struct clk *clkset_sclk_vpll_list[] = {
369 [0] = &clk_vpllsrc.clk,
370 [1] = &clk_fout_vpll,
373 static struct clksrc_sources clkset_sclk_vpll = {
374 .sources = clkset_sclk_vpll_list,
375 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
378 static struct clksrc_clk clk_sclk_vpll = {
383 .sources = &clkset_sclk_vpll,
384 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
387 static struct clk init_clocks_off[] = {
391 .parent = &clk_aclk_100.clk,
392 .enable = exynos4_clk_ip_peril_ctrl,
397 .enable = exynos4_clk_ip_cam_ctrl,
402 .enable = exynos4_clk_ip_cam_ctrl,
407 .enable = exynos4_clk_ip_cam_ctrl,
412 .enable = exynos4_clk_ip_cam_ctrl,
417 .enable = exynos4_clk_ip_cam_ctrl,
422 .enable = exynos4_clk_ip_cam_ctrl,
427 .enable = exynos4_clk_ip_lcd0_ctrl,
432 .enable = exynos4_clk_ip_lcd1_ctrl,
437 .parent = &clk_aclk_133.clk,
438 .enable = exynos4_clk_ip_fsys_ctrl,
443 .parent = &clk_aclk_133.clk,
444 .enable = exynos4_clk_ip_fsys_ctrl,
449 .parent = &clk_aclk_133.clk,
450 .enable = exynos4_clk_ip_fsys_ctrl,
455 .parent = &clk_aclk_133.clk,
456 .enable = exynos4_clk_ip_fsys_ctrl,
461 .parent = &clk_aclk_133.clk,
462 .enable = exynos4_clk_ip_fsys_ctrl,
467 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10),
472 .enable = exynos4_clk_ip_fsys_ctrl,
477 .enable = exynos4_clk_ip_fsys_ctrl,
482 .enable = exynos4_clk_ip_peril_ctrl,
483 .ctrlbit = (1 << 15),
487 .enable = exynos4_clk_ip_perir_ctrl,
488 .ctrlbit = (1 << 15),
492 .parent = &clk_aclk_100.clk,
493 .enable = exynos4_clk_ip_perir_ctrl,
494 .ctrlbit = (1 << 14),
498 .enable = exynos4_clk_ip_fsys_ctrl ,
499 .ctrlbit = (1 << 12),
503 .enable = exynos4_clk_ip_fsys_ctrl,
504 .ctrlbit = (1 << 13),
508 .enable = exynos4_clk_ip_peril_ctrl,
509 .ctrlbit = (1 << 16),
513 .enable = exynos4_clk_ip_peril_ctrl,
514 .ctrlbit = (1 << 17),
518 .enable = exynos4_clk_ip_peril_ctrl,
519 .ctrlbit = (1 << 18),
523 .enable = exynos4_clk_ip_peril_ctrl,
524 .ctrlbit = (1 << 19),
528 .enable = exynos4_clk_ip_peril_ctrl,
529 .ctrlbit = (1 << 20),
533 .enable = exynos4_clk_ip_peril_ctrl,
534 .ctrlbit = (1 << 21),
538 .enable = exynos4_clk_ip_peril_ctrl,
539 .ctrlbit = (1 << 27),
543 .enable = exynos4_clk_ip_image_ctrl,
548 .parent = &clk_aclk_100.clk,
549 .enable = exynos4_clk_ip_peril_ctrl,
554 .parent = &clk_aclk_100.clk,
555 .enable = exynos4_clk_ip_peril_ctrl,
560 .parent = &clk_aclk_100.clk,
561 .enable = exynos4_clk_ip_peril_ctrl,
566 .parent = &clk_aclk_100.clk,
567 .enable = exynos4_clk_ip_peril_ctrl,
572 .parent = &clk_aclk_100.clk,
573 .enable = exynos4_clk_ip_peril_ctrl,
574 .ctrlbit = (1 << 10),
578 .parent = &clk_aclk_100.clk,
579 .enable = exynos4_clk_ip_peril_ctrl,
580 .ctrlbit = (1 << 11),
584 .parent = &clk_aclk_100.clk,
585 .enable = exynos4_clk_ip_peril_ctrl,
586 .ctrlbit = (1 << 12),
590 .parent = &clk_aclk_100.clk,
591 .enable = exynos4_clk_ip_peril_ctrl,
592 .ctrlbit = (1 << 13),
596 static struct clk init_clocks[] = {
600 .enable = exynos4_clk_ip_peril_ctrl,
605 .enable = exynos4_clk_ip_peril_ctrl,
610 .enable = exynos4_clk_ip_peril_ctrl,
615 .enable = exynos4_clk_ip_peril_ctrl,
620 .enable = exynos4_clk_ip_peril_ctrl,
625 .enable = exynos4_clk_ip_peril_ctrl,
630 static struct clk *clkset_group_list[] = {
631 [0] = &clk_ext_xtal_mux,
633 [2] = &clk_sclk_hdmi27m,
634 [3] = &clk_sclk_usbphy0,
635 [4] = &clk_sclk_usbphy1,
636 [5] = &clk_sclk_hdmiphy,
637 [6] = &clk_mout_mpll.clk,
638 [7] = &clk_mout_epll.clk,
639 [8] = &clk_sclk_vpll.clk,
642 static struct clksrc_sources clkset_group = {
643 .sources = clkset_group_list,
644 .nr_sources = ARRAY_SIZE(clkset_group_list),
647 static struct clk *clkset_mout_g2d0_list[] = {
648 [0] = &clk_mout_mpll.clk,
649 [1] = &clk_sclk_apll.clk,
652 static struct clksrc_sources clkset_mout_g2d0 = {
653 .sources = clkset_mout_g2d0_list,
654 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
657 static struct clksrc_clk clk_mout_g2d0 = {
662 .sources = &clkset_mout_g2d0,
663 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
666 static struct clk *clkset_mout_g2d1_list[] = {
667 [0] = &clk_mout_epll.clk,
668 [1] = &clk_sclk_vpll.clk,
671 static struct clksrc_sources clkset_mout_g2d1 = {
672 .sources = clkset_mout_g2d1_list,
673 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
676 static struct clksrc_clk clk_mout_g2d1 = {
681 .sources = &clkset_mout_g2d1,
682 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
685 static struct clk *clkset_mout_g2d_list[] = {
686 [0] = &clk_mout_g2d0.clk,
687 [1] = &clk_mout_g2d1.clk,
690 static struct clksrc_sources clkset_mout_g2d = {
691 .sources = clkset_mout_g2d_list,
692 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
695 static struct clksrc_clk clk_dout_mmc0 = {
700 .sources = &clkset_group,
701 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
702 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
705 static struct clksrc_clk clk_dout_mmc1 = {
710 .sources = &clkset_group,
711 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
712 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
715 static struct clksrc_clk clk_dout_mmc2 = {
720 .sources = &clkset_group,
721 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
722 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
725 static struct clksrc_clk clk_dout_mmc3 = {
730 .sources = &clkset_group,
731 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
732 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
735 static struct clksrc_clk clk_dout_mmc4 = {
740 .sources = &clkset_group,
741 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
742 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
745 static struct clksrc_clk clksrcs[] = {
750 .enable = exynos4_clksrc_mask_peril0_ctrl,
753 .sources = &clkset_group,
754 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
755 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
760 .enable = exynos4_clksrc_mask_peril0_ctrl,
763 .sources = &clkset_group,
764 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
765 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
770 .enable = exynos4_clksrc_mask_peril0_ctrl,
773 .sources = &clkset_group,
774 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
775 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
780 .enable = exynos4_clksrc_mask_peril0_ctrl,
781 .ctrlbit = (1 << 12),
783 .sources = &clkset_group,
784 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
785 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
790 .enable = exynos4_clksrc_mask_peril0_ctrl,
791 .ctrlbit = (1 << 24),
793 .sources = &clkset_group,
794 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
795 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
800 .enable = exynos4_clksrc_mask_cam_ctrl,
801 .ctrlbit = (1 << 24),
803 .sources = &clkset_group,
804 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
805 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
810 .enable = exynos4_clksrc_mask_cam_ctrl,
811 .ctrlbit = (1 << 28),
813 .sources = &clkset_group,
814 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
815 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
820 .enable = exynos4_clksrc_mask_cam_ctrl,
821 .ctrlbit = (1 << 16),
823 .sources = &clkset_group,
824 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
825 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
830 .enable = exynos4_clksrc_mask_cam_ctrl,
831 .ctrlbit = (1 << 20),
833 .sources = &clkset_group,
834 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
835 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
840 .enable = exynos4_clksrc_mask_cam_ctrl,
843 .sources = &clkset_group,
844 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
845 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
850 .enable = exynos4_clksrc_mask_cam_ctrl,
853 .sources = &clkset_group,
854 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
855 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
860 .enable = exynos4_clksrc_mask_cam_ctrl,
863 .sources = &clkset_group,
864 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
865 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
870 .enable = exynos4_clksrc_mask_cam_ctrl,
871 .ctrlbit = (1 << 12),
873 .sources = &clkset_group,
874 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
875 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
880 .enable = exynos4_clksrc_mask_lcd0_ctrl,
883 .sources = &clkset_group,
884 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
885 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
890 .enable = exynos4_clksrc_mask_lcd1_ctrl,
893 .sources = &clkset_group,
894 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
895 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
900 .enable = exynos4_clksrc_mask_fsys_ctrl,
901 .ctrlbit = (1 << 24),
903 .sources = &clkset_mout_corebus,
904 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
905 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
910 .enable = exynos4_clksrc_mask_peril1_ctrl,
911 .ctrlbit = (1 << 16),
913 .sources = &clkset_group,
914 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
915 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
920 .enable = exynos4_clksrc_mask_peril1_ctrl,
921 .ctrlbit = (1 << 20),
923 .sources = &clkset_group,
924 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
925 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
930 .enable = exynos4_clksrc_mask_peril1_ctrl,
931 .ctrlbit = (1 << 24),
933 .sources = &clkset_group,
934 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
935 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
938 .name = "sclk_fimg2d",
941 .sources = &clkset_mout_g2d,
942 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
943 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
948 .parent = &clk_dout_mmc0.clk,
949 .enable = exynos4_clksrc_mask_fsys_ctrl,
952 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
957 .parent = &clk_dout_mmc1.clk,
958 .enable = exynos4_clksrc_mask_fsys_ctrl,
961 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
966 .parent = &clk_dout_mmc2.clk,
967 .enable = exynos4_clksrc_mask_fsys_ctrl,
970 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
975 .parent = &clk_dout_mmc3.clk,
976 .enable = exynos4_clksrc_mask_fsys_ctrl,
977 .ctrlbit = (1 << 12),
979 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
984 .parent = &clk_dout_mmc4.clk,
985 .enable = exynos4_clksrc_mask_fsys_ctrl,
986 .ctrlbit = (1 << 16),
988 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
992 /* Clock initialization code */
993 static struct clksrc_clk *sysclks[] = {
1024 static int xtal_rate;
1026 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1028 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1031 static struct clk_ops exynos4_fout_apll_ops = {
1032 .get_rate = exynos4_fout_apll_get_rate,
1035 void __init_or_cpufreq exynos4_setup_clocks(void)
1037 struct clk *xtal_clk;
1042 unsigned long vpllsrc;
1044 unsigned long armclk;
1045 unsigned long sclk_dmc;
1046 unsigned long aclk_200;
1047 unsigned long aclk_100;
1048 unsigned long aclk_160;
1049 unsigned long aclk_133;
1052 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1054 xtal_clk = clk_get(NULL, "xtal");
1055 BUG_ON(IS_ERR(xtal_clk));
1057 xtal = clk_get_rate(xtal_clk);
1063 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1065 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1066 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1067 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1068 __raw_readl(S5P_EPLL_CON1), pll_4600);
1070 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1071 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1072 __raw_readl(S5P_VPLL_CON1), pll_4650);
1074 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1075 clk_fout_mpll.rate = mpll;
1076 clk_fout_epll.rate = epll;
1077 clk_fout_vpll.rate = vpll;
1079 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1080 apll, mpll, epll, vpll);
1082 armclk = clk_get_rate(&clk_armclk.clk);
1083 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1085 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1086 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1087 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1088 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1090 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1091 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1092 armclk, sclk_dmc, aclk_200,
1093 aclk_100, aclk_160, aclk_133);
1095 clk_f.rate = armclk;
1096 clk_h.rate = sclk_dmc;
1097 clk_p.rate = aclk_100;
1099 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1100 s3c_set_clksrc(&clksrcs[ptr], true);
1103 static struct clk *clks[] __initdata = {
1104 /* Nothing here yet */
1107 void __init exynos4_register_clocks(void)
1111 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1113 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1114 s3c_register_clksrc(sysclks[ptr], 1);
1116 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1117 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1119 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1120 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));