1 /* linux/arch/arm/mach-exynos4/cpufreq.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - CPU frequency scaling support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/slab.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/cpufreq.h>
23 #include <mach/regs-clock.h>
24 #include <mach/regs-mem.h>
26 #include <plat/clock.h>
29 static struct clk *cpu_clk;
30 static struct clk *moutcore;
31 static struct clk *mout_mpll;
32 static struct clk *mout_apll;
34 static struct regulator *arm_regulator;
35 static struct regulator *int_regulator;
37 static struct cpufreq_freqs freqs;
38 static unsigned int memtype;
40 enum exynos4_memory_type {
46 enum cpufreq_level_index {
47 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50 static struct cpufreq_frequency_table exynos4_freq_table[] = {
55 {0, CPUFREQ_TABLE_END},
58 static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
60 * Clock divider value for following
61 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
62 * DIVATB, DIVPCLK_DBG, DIVAPLL }
66 { 0, 3, 7, 3, 3, 0, 1 },
69 { 0, 3, 7, 3, 3, 0, 1 },
72 { 0, 1, 3, 1, 3, 0, 1 },
75 { 0, 0, 1, 0, 3, 1, 1 },
78 static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
80 * Clock divider value for following
97 static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
99 * Clock divider value for following
100 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
101 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
105 { 3, 1, 1, 1, 1, 1, 3, 1 },
108 { 3, 1, 1, 1, 1, 1, 3, 1 },
110 /* DMC L2: 266.7MHz */
111 { 7, 1, 1, 2, 1, 1, 3, 1 },
114 { 7, 1, 1, 3, 1, 1, 3, 1 },
117 static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
119 * Clock divider value for following
120 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
123 /* ACLK200 L0: 200MHz */
126 /* ACLK200 L1: 200MHz */
129 /* ACLK200 L2: 160MHz */
132 /* ACLK200 L3: 133.3MHz */
136 static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
138 * Clock divider value for following
139 * { DIVGDL/R, DIVGPL/R }
142 /* ACLK_GDL/R L0: 200MHz */
145 /* ACLK_GDL/R L1: 200MHz */
148 /* ACLK_GDL/R L2: 160MHz */
151 /* ACLK_GDL/R L3: 133.3MHz */
155 struct cpufreq_voltage_table {
156 unsigned int index; /* any */
157 unsigned int arm_volt; /* uV */
158 unsigned int int_volt;
161 static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
181 static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
182 /* APLL FOUT L0: 1000MHz */
183 ((250 << 16) | (6 << 8) | 1),
185 /* APLL FOUT L1: 800MHz */
186 ((200 << 16) | (6 << 8) | 1),
188 /* APLL FOUT L2 : 400MHz */
189 ((200 << 16) | (6 << 8) | 2),
191 /* APLL FOUT L3: 100MHz */
192 ((200 << 16) | (6 << 8) | 4),
195 int exynos4_verify_speed(struct cpufreq_policy *policy)
197 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
200 unsigned int exynos4_getspeed(unsigned int cpu)
202 return clk_get_rate(cpu_clk) / 1000;
205 void exynos4_set_clkdiv(unsigned int div_index)
209 /* Change Divider - CPU0 */
211 tmp = __raw_readl(S5P_CLKDIV_CPU);
213 tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
214 S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
215 S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
216 S5P_CLKDIV_CPU0_APLL_MASK);
218 tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
219 (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
220 (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
221 (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
222 (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
223 (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
224 (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
226 __raw_writel(tmp, S5P_CLKDIV_CPU);
229 tmp = __raw_readl(S5P_CLKDIV_STATCPU);
230 } while (tmp & 0x1111111);
232 /* Change Divider - CPU1 */
234 tmp = __raw_readl(S5P_CLKDIV_CPU1);
236 tmp &= ~((0x7 << 4) | 0x7);
238 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
239 (clkdiv_cpu1[div_index][1] << 0));
241 __raw_writel(tmp, S5P_CLKDIV_CPU1);
244 tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
245 } while (tmp & 0x11);
247 /* Change Divider - DMC0 */
249 tmp = __raw_readl(S5P_CLKDIV_DMC0);
251 tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
252 S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
253 S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
254 S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
256 tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
257 (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
258 (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
259 (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
260 (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
261 (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
262 (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
263 (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
265 __raw_writel(tmp, S5P_CLKDIV_DMC0);
268 tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
269 } while (tmp & 0x11111111);
271 /* Change Divider - TOP */
273 tmp = __raw_readl(S5P_CLKDIV_TOP);
275 tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
276 S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
277 S5P_CLKDIV_TOP_ONENAND_MASK);
279 tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
280 (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
281 (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
282 (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
283 (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
285 __raw_writel(tmp, S5P_CLKDIV_TOP);
288 tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
289 } while (tmp & 0x11111);
291 /* Change Divider - LEFTBUS */
293 tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
295 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
297 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
298 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
300 __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
303 tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
304 } while (tmp & 0x11);
306 /* Change Divider - RIGHTBUS */
308 tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
310 tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
312 tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
313 (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
315 __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
318 tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
319 } while (tmp & 0x11);
322 static void exynos4_set_apll(unsigned int index)
326 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
327 clk_set_parent(moutcore, mout_mpll);
330 tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
331 >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
333 } while (tmp != 0x2);
335 /* 2. Set APLL Lock time */
336 __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
338 /* 3. Change PLL PMS values */
339 tmp = __raw_readl(S5P_APLL_CON0);
340 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
341 tmp |= exynos4_apll_pms_table[index];
342 __raw_writel(tmp, S5P_APLL_CON0);
344 /* 4. wait_lock_time */
346 tmp = __raw_readl(S5P_APLL_CON0);
347 } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
349 /* 5. MUX_CORE_SEL = APLL */
350 clk_set_parent(moutcore, mout_apll);
353 tmp = __raw_readl(S5P_CLKMUX_STATCPU);
354 tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
355 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358 static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
362 if (old_index > new_index) {
363 /* The frequency changing to L0 needs to change apll */
364 if (freqs.new == exynos4_freq_table[L0].frequency) {
365 /* 1. Change the system clock divider values */
366 exynos4_set_clkdiv(new_index);
368 /* 2. Change the apll m,p,s value */
369 exynos4_set_apll(new_index);
371 /* 1. Change the system clock divider values */
372 exynos4_set_clkdiv(new_index);
374 /* 2. Change just s value in apll m,p,s value */
375 tmp = __raw_readl(S5P_APLL_CON0);
377 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
378 __raw_writel(tmp, S5P_APLL_CON0);
382 else if (old_index < new_index) {
383 /* The frequency changing from L0 needs to change apll */
384 if (freqs.old == exynos4_freq_table[L0].frequency) {
385 /* 1. Change the apll m,p,s value */
386 exynos4_set_apll(new_index);
388 /* 2. Change the system clock divider values */
389 exynos4_set_clkdiv(new_index);
391 /* 1. Change just s value in apll m,p,s value */
392 tmp = __raw_readl(S5P_APLL_CON0);
394 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
395 __raw_writel(tmp, S5P_APLL_CON0);
397 /* 2. Change the system clock divider values */
398 exynos4_set_clkdiv(new_index);
403 static int exynos4_target(struct cpufreq_policy *policy,
404 unsigned int target_freq,
405 unsigned int relation)
407 unsigned int index, old_index;
408 unsigned int arm_volt, int_volt;
410 freqs.old = exynos4_getspeed(policy->cpu);
412 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
413 freqs.old, relation, &old_index))
416 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
417 target_freq, relation, &index))
420 freqs.new = exynos4_freq_table[index].frequency;
421 freqs.cpu = policy->cpu;
423 if (freqs.new == freqs.old)
426 /* get the voltage value */
427 arm_volt = exynos4_volt_table[index].arm_volt;
428 int_volt = exynos4_volt_table[index].int_volt;
430 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
432 /* control regulator */
433 if (freqs.new > freqs.old) {
435 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
436 regulator_set_voltage(int_regulator, int_volt, int_volt);
439 /* Clock Configuration Procedure */
440 exynos4_set_frequency(old_index, index);
442 /* control regulator */
443 if (freqs.new < freqs.old) {
445 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
446 regulator_set_voltage(int_regulator, int_volt, int_volt);
449 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
455 static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,
461 static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
467 static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
469 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
471 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
473 /* set the transition latency value */
474 policy->cpuinfo.transition_latency = 100000;
477 * EXYNOS4 multi-core processors has 2 cores
478 * that the frequency cannot be set independently.
479 * Each cpu is bound to the same speed.
480 * So the affected cpu is all of the cpus.
482 cpumask_setall(policy->cpus);
484 return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
487 static struct cpufreq_driver exynos4_driver = {
488 .flags = CPUFREQ_STICKY,
489 .verify = exynos4_verify_speed,
490 .target = exynos4_target,
491 .get = exynos4_getspeed,
492 .init = exynos4_cpufreq_cpu_init,
493 .name = "exynos4_cpufreq",
495 .suspend = exynos4_cpufreq_suspend,
496 .resume = exynos4_cpufreq_resume,
500 static int __init exynos4_cpufreq_init(void)
502 cpu_clk = clk_get(NULL, "armclk");
504 return PTR_ERR(cpu_clk);
506 moutcore = clk_get(NULL, "moutcore");
507 if (IS_ERR(moutcore))
510 mout_mpll = clk_get(NULL, "mout_mpll");
511 if (IS_ERR(mout_mpll))
514 mout_apll = clk_get(NULL, "mout_apll");
515 if (IS_ERR(mout_apll))
518 arm_regulator = regulator_get(NULL, "vdd_arm");
519 if (IS_ERR(arm_regulator)) {
520 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
524 int_regulator = regulator_get(NULL, "vdd_int");
525 if (IS_ERR(int_regulator)) {
526 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
532 * Because DVFS level is different according to DRAM type.
534 memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
535 memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
536 memtype &= S5P_DMC0_MEMTYPE_MASK;
538 if ((memtype < DDR2) && (memtype > DDR3)) {
539 printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
542 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
545 return cpufreq_register_driver(&exynos4_driver);
548 if (!IS_ERR(cpu_clk))
551 if (!IS_ERR(moutcore))
554 if (!IS_ERR(mout_mpll))
557 if (!IS_ERR(mout_apll))
560 if (!IS_ERR(arm_regulator))
561 regulator_put(arm_regulator);
563 if (!IS_ERR(int_regulator))
564 regulator_put(int_regulator);
566 printk(KERN_ERR "%s: failed initialization\n", __func__);
570 late_initcall(exynos4_cpufreq_init);