2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
10 #include <linux/cpu.h>
11 #include <linux/delay.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <asm/cacheflush.h>
16 #include <asm/smp_plat.h>
19 /* Sysctrl registers in Hi3620 SoC */
22 #define SCPERPWREN 0xd0
23 #define SCPERPWRDIS 0xd4
24 #define SCCPUCOREEN 0xf4
25 #define SCCPUCOREDIS 0xf8
26 #define SCPERCTRL0 0x200
27 #define SCCPURSTEN 0x410
28 #define SCCPURSTDIS 0x414
31 * bit definition in SCISOEN/SCPERPWREN/...
33 * CPU2_ISO_CTRL (1 << 5)
34 * CPU3_ISO_CTRL (1 << 6)
37 #define CPU2_ISO_CTRL (1 << 5)
40 * bit definition in SCPERCTRL0
42 * CPU0_WFI_MASK_CFG (1 << 28)
43 * CPU1_WFI_MASK_CFG (1 << 29)
46 #define CPU0_WFI_MASK_CFG (1 << 28)
49 * bit definition in SCCPURSTEN/...
51 * CPU0_SRST_REQ_EN (1 << 0)
52 * CPU1_SRST_REQ_EN (1 << 1)
55 #define CPU0_HPM_SRST_REQ_EN (1 << 22)
56 #define CPU0_DBG_SRST_REQ_EN (1 << 12)
57 #define CPU0_NEON_SRST_REQ_EN (1 << 4)
58 #define CPU0_SRST_REQ_EN (1 << 0)
60 #define HIX5HD2_PERI_CRG20 0x50
61 #define CRG20_CPU1_RESET (1 << 17)
63 #define HIX5HD2_PERI_PMC0 0x1000
64 #define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
65 #define PMC0_CPU1_PMC_ENABLE (1 << 7)
66 #define PMC0_CPU1_POWERDOWN (1 << 3)
68 #define HIP01_PERI9 0x50
69 #define PERI9_CPU1_RESET (1 << 1)
76 static void __iomem *ctrl_base;
79 static void set_cpu_hi3620(int cpu, bool enable)
85 if ((cpu == 2) || (cpu == 3))
86 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
87 ctrl_base + SCPERPWREN);
91 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
94 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
98 val |= CPU0_HPM_SRST_REQ_EN;
99 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
102 if ((cpu == 2) || (cpu == 3))
103 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
104 ctrl_base + SCISODIS);
108 val = readl_relaxed(ctrl_base + SCPERCTRL0);
109 val &= ~(CPU0_WFI_MASK_CFG << cpu);
110 writel_relaxed(val, ctrl_base + SCPERCTRL0);
113 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
114 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
115 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
118 val = readl_relaxed(ctrl_base + SCPERCTRL0);
119 val |= (CPU0_WFI_MASK_CFG << cpu);
120 writel_relaxed(val, ctrl_base + SCPERCTRL0);
123 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
125 if ((cpu == 2) || (cpu == 3)) {
127 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
128 ctrl_base + SCISOEN);
133 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
134 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
135 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
137 if ((cpu == 2) || (cpu == 3)) {
139 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
140 ctrl_base + SCPERPWRDIS);
146 static int hi3xxx_hotplug_init(void)
148 struct device_node *node;
150 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
152 ctrl_base = of_iomap(node, 0);
160 void hi3xxx_set_cpu(int cpu, bool enable)
163 if (hi3xxx_hotplug_init() < 0)
167 if (id == HI3620_CTRL)
168 set_cpu_hi3620(cpu, enable);
171 static bool hix5hd2_hotplug_init(void)
173 struct device_node *np;
175 np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
177 ctrl_base = of_iomap(np, 0);
183 void hix5hd2_set_cpu(int cpu, bool enable)
188 if (!hix5hd2_hotplug_init())
193 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
194 val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
195 val |= PMC0_CPU1_PMC_ENABLE;
196 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
198 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
199 val &= ~CRG20_CPU1_RESET;
200 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
202 /* power down cpu1 */
203 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
204 val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
205 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
206 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
209 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
210 val |= CRG20_CPU1_RESET;
211 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
215 void hip01_set_cpu(int cpu, bool enable)
218 struct device_node *np;
221 np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
223 ctrl_base = of_iomap(np, 0);
230 temp = readl_relaxed(ctrl_base + HIP01_PERI9);
231 temp |= PERI9_CPU1_RESET;
232 writel_relaxed(temp, ctrl_base + HIP01_PERI9);
236 /* unreset on CPU1 */
237 temp = readl_relaxed(ctrl_base + HIP01_PERI9);
238 temp &= ~PERI9_CPU1_RESET;
239 writel_relaxed(temp, ctrl_base + HIP01_PERI9);
243 static inline void cpu_enter_lowpower(void)
250 * Turn off coherency and L1 D-cache
253 " mrc p15, 0, %0, c1, c0, 1\n"
254 " bic %0, %0, #0x40\n"
255 " mcr p15, 0, %0, c1, c0, 1\n"
256 " mrc p15, 0, %0, c1, c0, 0\n"
257 " bic %0, %0, #0x04\n"
258 " mcr p15, 0, %0, c1, c0, 0\n"
264 #ifdef CONFIG_HOTPLUG_CPU
265 void hi3xxx_cpu_die(unsigned int cpu)
267 cpu_enter_lowpower();
268 hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
271 /* We should have never returned from idle */
272 panic("cpu %d unexpectedly exit from shutdown\n", cpu);
275 int hi3xxx_cpu_kill(unsigned int cpu)
277 unsigned long timeout = jiffies + msecs_to_jiffies(50);
279 while (hi3xxx_get_cpu_jump(cpu))
280 if (time_after(jiffies, timeout))
282 hi3xxx_set_cpu(cpu, false);
286 void hix5hd2_cpu_die(unsigned int cpu)
289 hix5hd2_set_cpu(cpu, false);