2 #include <linux/clk-provider.h>
4 #include <linux/slab.h>
5 #include <linux/kernel.h>
15 * @clk_hw clock source
16 * @parent the parent clock name
17 * @base base address of pll registers
19 * PLL clock version 1, found on i.MX1/21/25/27/31/35
26 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
28 static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
29 unsigned long parent_rate)
31 struct clk_pllv1 *pll = to_clk_pllv1(hw);
34 unsigned int mfi, mfn, mfd, pd;
38 reg = readl(pll->base);
41 * Get the resulting clock rate from a PLL register value and the input
42 * frequency. PLLs with this register layout can be found on i.MX1,
43 * i.MX21, i.MX27 and i,MX31
45 * mfi + mfn / (mfd + 1)
46 * f = 2 * f_ref * --------------------
50 mfi = (reg >> 10) & 0xf;
52 mfd = (reg >> 16) & 0x3ff;
53 pd = (reg >> 26) & 0xf;
55 mfi = mfi <= 5 ? 5 : mfi;
60 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
61 * 2's complements number
63 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
64 mfn_abs = 0x400 - mfn;
66 rate = parent_rate * 2;
69 ll = (unsigned long long)rate * mfn_abs;
73 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
76 ll = (rate * mfi) + ll;
81 static struct clk_ops clk_pllv1_ops = {
82 .recalc_rate = clk_pllv1_recalc_rate,
85 struct clk *imx_clk_pllv1(const char *name, const char *parent,
88 struct clk_pllv1 *pll;
90 struct clk_init_data init;
92 pll = kmalloc(sizeof(*pll), GFP_KERNEL);
94 return ERR_PTR(-ENOMEM);
99 init.ops = &clk_pllv1_ops;
101 init.parent_names = &parent;
102 init.num_parents = 1;
104 pll->hw.init = &init;
106 clk = clk_register(NULL, &pll->hw);