2 #include <linux/clk-provider.h>
4 #include <linux/slab.h>
5 #include <linux/kernel.h>
15 * @clk_hw clock source
16 * @parent the parent clock name
17 * @base base address of pll registers
19 * PLL clock version 1, found on i.MX1/21/25/27/31/35
23 #define MFN_SIGN (BIT(MFN_BITS - 1))
24 #define MFN_MASK (MFN_SIGN - 1)
31 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
33 static inline bool mfn_is_negative(unsigned int mfn)
35 return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
38 static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
39 unsigned long parent_rate)
41 struct clk_pllv1 *pll = to_clk_pllv1(hw);
44 unsigned int mfi, mfn, mfd, pd;
48 reg = readl(pll->base);
51 * Get the resulting clock rate from a PLL register value and the input
52 * frequency. PLLs with this register layout can be found on i.MX1,
53 * i.MX21, i.MX27 and i,MX31
55 * mfi + mfn / (mfd + 1)
56 * f = 2 * f_ref * --------------------
60 mfi = (reg >> 10) & 0xf;
62 mfd = (reg >> 16) & 0x3ff;
63 pd = (reg >> 26) & 0xf;
65 mfi = mfi <= 5 ? 5 : mfi;
70 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
71 * 2's complements number.
72 * On i.MX27 the bit 9 is the sign bit.
74 if (mfn_is_negative(mfn)) {
76 mfn_abs = mfn & MFN_MASK;
78 mfn_abs = BIT(MFN_BITS) - mfn;
81 rate = parent_rate * 2;
84 ll = (unsigned long long)rate * mfn_abs;
88 if (mfn_is_negative(mfn))
91 ll = (rate * mfi) + ll;
96 static struct clk_ops clk_pllv1_ops = {
97 .recalc_rate = clk_pllv1_recalc_rate,
100 struct clk *imx_clk_pllv1(const char *name, const char *parent,
103 struct clk_pllv1 *pll;
105 struct clk_init_data init;
107 pll = kmalloc(sizeof(*pll), GFP_KERNEL);
109 return ERR_PTR(-ENOMEM);
114 init.ops = &clk_pllv1_ops;
116 init.parent_names = &parent;
117 init.num_parents = 1;
119 pll->hw.init = &init;
121 clk = clk_register(NULL, &pll->hw);