2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_ENABLE (0x1 << 13)
26 #define BM_PLL_BYPASS (0x1 << 16)
27 #define BM_PLL_LOCK (0x1 << 31)
30 * struct clk_pllv3 - IMX PLL clock version 3
31 * @clk_hw: clock source
32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL
34 * @div_mask: mask of divider bits
36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
37 * is actually a multiplier, and always sits at bit 0.
46 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
48 static int clk_pllv3_prepare(struct clk_hw *hw)
50 struct clk_pllv3 *pll = to_clk_pllv3(hw);
51 unsigned long timeout = jiffies + msecs_to_jiffies(10);
54 val = readl_relaxed(pll->base);
55 val &= ~BM_PLL_BYPASS;
60 writel_relaxed(val, pll->base);
62 /* Wait for PLL to lock */
63 while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
64 if (time_after(jiffies, timeout))
70 static void clk_pllv3_unprepare(struct clk_hw *hw)
72 struct clk_pllv3 *pll = to_clk_pllv3(hw);
75 val = readl_relaxed(pll->base);
81 writel_relaxed(val, pll->base);
84 static int clk_pllv3_enable(struct clk_hw *hw)
86 struct clk_pllv3 *pll = to_clk_pllv3(hw);
89 val = readl_relaxed(pll->base);
91 writel_relaxed(val, pll->base);
96 static void clk_pllv3_disable(struct clk_hw *hw)
98 struct clk_pllv3 *pll = to_clk_pllv3(hw);
101 val = readl_relaxed(pll->base);
102 val &= ~BM_PLL_ENABLE;
103 writel_relaxed(val, pll->base);
106 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
107 unsigned long parent_rate)
109 struct clk_pllv3 *pll = to_clk_pllv3(hw);
110 u32 div = readl_relaxed(pll->base) & pll->div_mask;
112 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
115 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
116 unsigned long *prate)
118 unsigned long parent_rate = *prate;
120 return (rate >= parent_rate * 22) ? parent_rate * 22 :
124 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
125 unsigned long parent_rate)
127 struct clk_pllv3 *pll = to_clk_pllv3(hw);
130 if (rate == parent_rate * 22)
132 else if (rate == parent_rate * 20)
137 val = readl_relaxed(pll->base);
138 val &= ~pll->div_mask;
140 writel_relaxed(val, pll->base);
145 static const struct clk_ops clk_pllv3_ops = {
146 .prepare = clk_pllv3_prepare,
147 .unprepare = clk_pllv3_unprepare,
148 .enable = clk_pllv3_enable,
149 .disable = clk_pllv3_disable,
150 .recalc_rate = clk_pllv3_recalc_rate,
151 .round_rate = clk_pllv3_round_rate,
152 .set_rate = clk_pllv3_set_rate,
155 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
156 unsigned long parent_rate)
158 struct clk_pllv3 *pll = to_clk_pllv3(hw);
159 u32 div = readl_relaxed(pll->base) & pll->div_mask;
161 return parent_rate * div / 2;
164 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
165 unsigned long *prate)
167 unsigned long parent_rate = *prate;
168 unsigned long min_rate = parent_rate * 54 / 2;
169 unsigned long max_rate = parent_rate * 108 / 2;
174 else if (rate < min_rate)
176 div = rate * 2 / parent_rate;
178 return parent_rate * div / 2;
181 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
182 unsigned long parent_rate)
184 struct clk_pllv3 *pll = to_clk_pllv3(hw);
185 unsigned long min_rate = parent_rate * 54 / 2;
186 unsigned long max_rate = parent_rate * 108 / 2;
189 if (rate < min_rate || rate > max_rate)
192 div = rate * 2 / parent_rate;
193 val = readl_relaxed(pll->base);
194 val &= ~pll->div_mask;
196 writel_relaxed(val, pll->base);
201 static const struct clk_ops clk_pllv3_sys_ops = {
202 .prepare = clk_pllv3_prepare,
203 .unprepare = clk_pllv3_unprepare,
204 .enable = clk_pllv3_enable,
205 .disable = clk_pllv3_disable,
206 .recalc_rate = clk_pllv3_sys_recalc_rate,
207 .round_rate = clk_pllv3_sys_round_rate,
208 .set_rate = clk_pllv3_sys_set_rate,
211 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
212 unsigned long parent_rate)
214 struct clk_pllv3 *pll = to_clk_pllv3(hw);
215 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
216 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
217 u32 div = readl_relaxed(pll->base) & pll->div_mask;
219 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
222 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
223 unsigned long *prate)
225 unsigned long parent_rate = *prate;
226 unsigned long min_rate = parent_rate * 27;
227 unsigned long max_rate = parent_rate * 54;
229 u32 mfn, mfd = 1000000;
234 else if (rate < min_rate)
237 div = rate / parent_rate;
238 temp64 = (u64) (rate - div * parent_rate);
240 do_div(temp64, parent_rate);
243 return parent_rate * div + parent_rate / mfd * mfn;
246 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
247 unsigned long parent_rate)
249 struct clk_pllv3 *pll = to_clk_pllv3(hw);
250 unsigned long min_rate = parent_rate * 27;
251 unsigned long max_rate = parent_rate * 54;
253 u32 mfn, mfd = 1000000;
256 if (rate < min_rate || rate > max_rate)
259 div = rate / parent_rate;
260 temp64 = (u64) (rate - div * parent_rate);
262 do_div(temp64, parent_rate);
265 val = readl_relaxed(pll->base);
266 val &= ~pll->div_mask;
268 writel_relaxed(val, pll->base);
269 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
270 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
275 static const struct clk_ops clk_pllv3_av_ops = {
276 .prepare = clk_pllv3_prepare,
277 .unprepare = clk_pllv3_unprepare,
278 .enable = clk_pllv3_enable,
279 .disable = clk_pllv3_disable,
280 .recalc_rate = clk_pllv3_av_recalc_rate,
281 .round_rate = clk_pllv3_av_round_rate,
282 .set_rate = clk_pllv3_av_set_rate,
285 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
286 unsigned long parent_rate)
291 static const struct clk_ops clk_pllv3_enet_ops = {
292 .prepare = clk_pllv3_prepare,
293 .unprepare = clk_pllv3_unprepare,
294 .enable = clk_pllv3_enable,
295 .disable = clk_pllv3_disable,
296 .recalc_rate = clk_pllv3_enet_recalc_rate,
299 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
300 const char *parent_name, void __iomem *base,
303 struct clk_pllv3 *pll;
304 const struct clk_ops *ops;
306 struct clk_init_data init;
308 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
310 return ERR_PTR(-ENOMEM);
314 ops = &clk_pllv3_sys_ops;
317 ops = &clk_pllv3_ops;
318 pll->powerup_set = true;
321 ops = &clk_pllv3_av_ops;
324 ops = &clk_pllv3_enet_ops;
327 ops = &clk_pllv3_ops;
330 pll->div_mask = div_mask;
335 init.parent_names = &parent_name;
336 init.num_parents = 1;
338 pll->hw.init = &init;
340 clk = clk_register(NULL, &pll->hw);