2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_ENABLE (0x1 << 13)
26 #define BM_PLL_BYPASS (0x1 << 16)
27 #define BM_PLL_LOCK (0x1 << 31)
30 * struct clk_pllv3 - IMX PLL clock version 3
31 * @clk_hw: clock source
32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL
34 * @div_mask: mask of divider bits
36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
37 * is actually a multiplier, and always sits at bit 0.
46 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
48 static int clk_pllv3_prepare(struct clk_hw *hw)
50 struct clk_pllv3 *pll = to_clk_pllv3(hw);
51 unsigned long timeout;
54 val = readl_relaxed(pll->base);
55 val &= ~BM_PLL_BYPASS;
60 writel_relaxed(val, pll->base);
62 timeout = jiffies + msecs_to_jiffies(10);
63 /* Wait for PLL to lock */
65 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
67 if (time_after(jiffies, timeout))
71 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
77 static void clk_pllv3_unprepare(struct clk_hw *hw)
79 struct clk_pllv3 *pll = to_clk_pllv3(hw);
82 val = readl_relaxed(pll->base);
88 writel_relaxed(val, pll->base);
91 static int clk_pllv3_enable(struct clk_hw *hw)
93 struct clk_pllv3 *pll = to_clk_pllv3(hw);
96 val = readl_relaxed(pll->base);
98 writel_relaxed(val, pll->base);
103 static void clk_pllv3_disable(struct clk_hw *hw)
105 struct clk_pllv3 *pll = to_clk_pllv3(hw);
108 val = readl_relaxed(pll->base);
109 val &= ~BM_PLL_ENABLE;
110 writel_relaxed(val, pll->base);
113 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
114 unsigned long parent_rate)
116 struct clk_pllv3 *pll = to_clk_pllv3(hw);
117 u32 div = readl_relaxed(pll->base) & pll->div_mask;
119 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
122 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
123 unsigned long *prate)
125 unsigned long parent_rate = *prate;
127 return (rate >= parent_rate * 22) ? parent_rate * 22 :
131 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
132 unsigned long parent_rate)
134 struct clk_pllv3 *pll = to_clk_pllv3(hw);
137 if (rate == parent_rate * 22)
139 else if (rate == parent_rate * 20)
144 val = readl_relaxed(pll->base);
145 val &= ~pll->div_mask;
147 writel_relaxed(val, pll->base);
152 static const struct clk_ops clk_pllv3_ops = {
153 .prepare = clk_pllv3_prepare,
154 .unprepare = clk_pllv3_unprepare,
155 .enable = clk_pllv3_enable,
156 .disable = clk_pllv3_disable,
157 .recalc_rate = clk_pllv3_recalc_rate,
158 .round_rate = clk_pllv3_round_rate,
159 .set_rate = clk_pllv3_set_rate,
162 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
163 unsigned long parent_rate)
165 struct clk_pllv3 *pll = to_clk_pllv3(hw);
166 u32 div = readl_relaxed(pll->base) & pll->div_mask;
168 return parent_rate * div / 2;
171 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
172 unsigned long *prate)
174 unsigned long parent_rate = *prate;
175 unsigned long min_rate = parent_rate * 54 / 2;
176 unsigned long max_rate = parent_rate * 108 / 2;
181 else if (rate < min_rate)
183 div = rate * 2 / parent_rate;
185 return parent_rate * div / 2;
188 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
189 unsigned long parent_rate)
191 struct clk_pllv3 *pll = to_clk_pllv3(hw);
192 unsigned long min_rate = parent_rate * 54 / 2;
193 unsigned long max_rate = parent_rate * 108 / 2;
196 if (rate < min_rate || rate > max_rate)
199 div = rate * 2 / parent_rate;
200 val = readl_relaxed(pll->base);
201 val &= ~pll->div_mask;
203 writel_relaxed(val, pll->base);
208 static const struct clk_ops clk_pllv3_sys_ops = {
209 .prepare = clk_pllv3_prepare,
210 .unprepare = clk_pllv3_unprepare,
211 .enable = clk_pllv3_enable,
212 .disable = clk_pllv3_disable,
213 .recalc_rate = clk_pllv3_sys_recalc_rate,
214 .round_rate = clk_pllv3_sys_round_rate,
215 .set_rate = clk_pllv3_sys_set_rate,
218 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
219 unsigned long parent_rate)
221 struct clk_pllv3 *pll = to_clk_pllv3(hw);
222 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
223 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
224 u32 div = readl_relaxed(pll->base) & pll->div_mask;
226 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
229 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
230 unsigned long *prate)
232 unsigned long parent_rate = *prate;
233 unsigned long min_rate = parent_rate * 27;
234 unsigned long max_rate = parent_rate * 54;
236 u32 mfn, mfd = 1000000;
241 else if (rate < min_rate)
244 div = rate / parent_rate;
245 temp64 = (u64) (rate - div * parent_rate);
247 do_div(temp64, parent_rate);
250 return parent_rate * div + parent_rate / mfd * mfn;
253 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
254 unsigned long parent_rate)
256 struct clk_pllv3 *pll = to_clk_pllv3(hw);
257 unsigned long min_rate = parent_rate * 27;
258 unsigned long max_rate = parent_rate * 54;
260 u32 mfn, mfd = 1000000;
263 if (rate < min_rate || rate > max_rate)
266 div = rate / parent_rate;
267 temp64 = (u64) (rate - div * parent_rate);
269 do_div(temp64, parent_rate);
272 val = readl_relaxed(pll->base);
273 val &= ~pll->div_mask;
275 writel_relaxed(val, pll->base);
276 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
277 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
282 static const struct clk_ops clk_pllv3_av_ops = {
283 .prepare = clk_pllv3_prepare,
284 .unprepare = clk_pllv3_unprepare,
285 .enable = clk_pllv3_enable,
286 .disable = clk_pllv3_disable,
287 .recalc_rate = clk_pllv3_av_recalc_rate,
288 .round_rate = clk_pllv3_av_round_rate,
289 .set_rate = clk_pllv3_av_set_rate,
292 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
293 unsigned long parent_rate)
298 static const struct clk_ops clk_pllv3_enet_ops = {
299 .prepare = clk_pllv3_prepare,
300 .unprepare = clk_pllv3_unprepare,
301 .enable = clk_pllv3_enable,
302 .disable = clk_pllv3_disable,
303 .recalc_rate = clk_pllv3_enet_recalc_rate,
306 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
307 const char *parent_name, void __iomem *base,
310 struct clk_pllv3 *pll;
311 const struct clk_ops *ops;
313 struct clk_init_data init;
315 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
317 return ERR_PTR(-ENOMEM);
321 ops = &clk_pllv3_sys_ops;
324 ops = &clk_pllv3_ops;
325 pll->powerup_set = true;
328 ops = &clk_pllv3_av_ops;
331 ops = &clk_pllv3_enet_ops;
334 ops = &clk_pllv3_ops;
337 pll->div_mask = div_mask;
342 init.parent_names = &parent_name;
343 init.num_parents = 1;
345 pll->hw.init = &init;
347 clk = clk_register(NULL, &pll->hw);