2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/clk.h>
24 #include <linux/clkdev.h>
26 #include <mach/clock.h>
27 #include <mach/hardware.h>
28 #include <mach/common.h>
30 #include "crmregs-imx3.h"
32 #ifdef HAVE_SET_RATE_SUPPORT
33 static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
35 u32 min_pre, temp_pre, old_err, err;
37 min_pre = (div - 1) / maxpost + 1;
40 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
41 if (div > (temp_pre * maxpost))
44 if (div < (temp_pre * temp_pre))
62 *post = (div + *pre - 1) / *pre;
65 /* get the best values for a 3-bit divider combined with a 6-bit divider */
66 static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
71 } else if (div >= 64) {
72 calc_dividers(div, pre, post, 64);
73 } else if (div <= 8) {
82 /* get the best values for two cascaded 3-bit dividers */
83 static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
88 calc_dividers(div, pre, post, 8);
96 static unsigned long get_rate_mpll(void)
98 ulong mpctl = __raw_readl(MX35_CCM_MPCTL);
100 return mxc_decode_pll(mpctl, 24000000);
103 static unsigned long get_rate_ppll(void)
105 ulong ppctl = __raw_readl(MX35_CCM_PPCTL);
107 return mxc_decode_pll(ppctl, 24000000);
111 unsigned char arm, ahb, sel;
114 static struct arm_ahb_div clk_consumer[] = {
115 { .arm = 1, .ahb = 4, .sel = 0},
116 { .arm = 1, .ahb = 3, .sel = 1},
117 { .arm = 2, .ahb = 2, .sel = 0},
118 { .arm = 0, .ahb = 0, .sel = 0},
119 { .arm = 0, .ahb = 0, .sel = 0},
120 { .arm = 0, .ahb = 0, .sel = 0},
121 { .arm = 4, .ahb = 1, .sel = 0},
122 { .arm = 1, .ahb = 5, .sel = 0},
123 { .arm = 1, .ahb = 8, .sel = 0},
124 { .arm = 1, .ahb = 6, .sel = 1},
125 { .arm = 2, .ahb = 4, .sel = 0},
126 { .arm = 0, .ahb = 0, .sel = 0},
127 { .arm = 0, .ahb = 0, .sel = 0},
128 { .arm = 0, .ahb = 0, .sel = 0},
129 { .arm = 4, .ahb = 2, .sel = 0},
130 { .arm = 0, .ahb = 0, .sel = 0},
133 static unsigned long get_rate_arm(void)
135 unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
136 struct arm_ahb_div *aad;
137 unsigned long fref = get_rate_mpll();
139 aad = &clk_consumer[(pdr0 >> 16) & 0xf];
143 return fref / aad->arm;
146 static unsigned long get_rate_ahb(struct clk *clk)
148 unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
149 struct arm_ahb_div *aad;
150 unsigned long fref = get_rate_arm();
152 aad = &clk_consumer[(pdr0 >> 16) & 0xf];
154 return fref / aad->ahb;
157 static unsigned long get_rate_ipg(struct clk *clk)
159 return get_rate_ahb(NULL) >> 1;
162 static unsigned long get_rate_uart(struct clk *clk)
164 unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
165 unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
166 unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
168 if (pdr3 & (1 << 14))
169 return get_rate_arm() / div;
171 return get_rate_ppll() / div;
174 static unsigned long get_rate_sdhc(struct clk *clk)
176 unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
177 unsigned long div, rate;
180 rate = get_rate_arm();
182 rate = get_rate_ppll();
190 div = (pdr3 >> 8) & 0x3f;
193 div = (pdr3 >> 16) & 0x3f;
197 return rate / (div + 1);
200 static unsigned long get_rate_mshc(struct clk *clk)
202 unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1);
203 unsigned long div1, div2, rate;
206 rate = get_rate_arm();
208 rate = get_rate_ppll();
210 div1 = (pdr1 >> 29) & 0x7;
211 div2 = (pdr1 >> 22) & 0x3f;
213 return rate / ((div1 + 1) * (div2 + 1));
216 static unsigned long get_rate_ssi(struct clk *clk)
218 unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
219 unsigned long div1, div2, rate;
222 rate = get_rate_arm();
224 rate = get_rate_ppll();
230 div2 = (pdr2 >> 24) & 0x7;
233 div1 = (pdr2 >> 8) & 0x3f;
234 div2 = (pdr2 >> 27) & 0x7;
238 return rate / ((div1 + 1) * (div2 + 1));
241 static unsigned long get_rate_csi(struct clk *clk)
243 unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
247 rate = get_rate_arm();
249 rate = get_rate_ppll();
251 return rate / (((pdr2 >> 16) & 0x3f) + 1);
254 static unsigned long get_rate_otg(struct clk *clk)
256 unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
260 rate = get_rate_arm();
262 rate = get_rate_ppll();
264 return rate / (((pdr4 >> 22) & 0x3f) + 1);
267 static unsigned long get_rate_ipg_per(struct clk *clk)
269 unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
270 unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
273 if (pdr0 & (1 << 26)) {
274 div = (pdr4 >> 16) & 0x3f;
275 return get_rate_arm() / (div + 1);
277 div = (pdr0 >> 12) & 0x7;
278 return get_rate_ahb(NULL) / (div + 1);
282 static unsigned long get_rate_hsp(struct clk *clk)
284 unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03;
285 unsigned long fref = get_rate_mpll();
287 if (fref > 400 * 1000 * 1000) {
309 static int clk_cgr_enable(struct clk *clk)
313 reg = __raw_readl(clk->enable_reg);
314 reg |= 3 << clk->enable_shift;
315 __raw_writel(reg, clk->enable_reg);
320 static void clk_cgr_disable(struct clk *clk)
324 reg = __raw_readl(clk->enable_reg);
325 reg &= ~(3 << clk->enable_shift);
326 __raw_writel(reg, clk->enable_reg);
329 #define DEFINE_CLOCK(name, i, er, es, gr, sr) \
330 static struct clk name = { \
333 .enable_shift = es, \
336 .enable = clk_cgr_enable, \
337 .disable = clk_cgr_disable, \
340 DEFINE_CLOCK(asrc_clk, 0, MX35_CCM_CGR0, 0, NULL, NULL);
341 DEFINE_CLOCK(pata_clk, 0, MX35_CCM_CGR0, 2, get_rate_ipg, NULL);
342 /* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0, 4, NULL, NULL); */
343 DEFINE_CLOCK(can1_clk, 0, MX35_CCM_CGR0, 6, get_rate_ipg, NULL);
344 DEFINE_CLOCK(can2_clk, 1, MX35_CCM_CGR0, 8, get_rate_ipg, NULL);
345 DEFINE_CLOCK(cspi1_clk, 0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
346 DEFINE_CLOCK(cspi2_clk, 1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
347 DEFINE_CLOCK(ect_clk, 0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
348 DEFINE_CLOCK(edio_clk, 0, MX35_CCM_CGR0, 16, NULL, NULL);
349 DEFINE_CLOCK(emi_clk, 0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL);
350 DEFINE_CLOCK(epit1_clk, 0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL);
351 DEFINE_CLOCK(epit2_clk, 1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL);
352 DEFINE_CLOCK(esai_clk, 0, MX35_CCM_CGR0, 24, NULL, NULL);
353 DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL);
354 DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL);
355 DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL);
357 DEFINE_CLOCK(fec_clk, 0, MX35_CCM_CGR1, 0, get_rate_ipg, NULL);
358 DEFINE_CLOCK(gpio1_clk, 0, MX35_CCM_CGR1, 2, NULL, NULL);
359 DEFINE_CLOCK(gpio2_clk, 1, MX35_CCM_CGR1, 4, NULL, NULL);
360 DEFINE_CLOCK(gpio3_clk, 2, MX35_CCM_CGR1, 6, NULL, NULL);
361 DEFINE_CLOCK(gpt_clk, 0, MX35_CCM_CGR1, 8, get_rate_ipg, NULL);
362 DEFINE_CLOCK(i2c1_clk, 0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL);
363 DEFINE_CLOCK(i2c2_clk, 1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL);
364 DEFINE_CLOCK(i2c3_clk, 2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL);
365 DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL);
366 DEFINE_CLOCK(ipu_clk, 0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL);
367 DEFINE_CLOCK(kpp_clk, 0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL);
368 DEFINE_CLOCK(mlb_clk, 0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL);
369 DEFINE_CLOCK(mshc_clk, 0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL);
370 DEFINE_CLOCK(owire_clk, 0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL);
371 DEFINE_CLOCK(pwm_clk, 0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL);
372 DEFINE_CLOCK(rngc_clk, 0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL);
374 DEFINE_CLOCK(rtc_clk, 0, MX35_CCM_CGR2, 0, get_rate_ipg, NULL);
375 DEFINE_CLOCK(rtic_clk, 0, MX35_CCM_CGR2, 2, get_rate_ahb, NULL);
376 DEFINE_CLOCK(scc_clk, 0, MX35_CCM_CGR2, 4, get_rate_ipg, NULL);
377 DEFINE_CLOCK(sdma_clk, 0, MX35_CCM_CGR2, 6, NULL, NULL);
378 DEFINE_CLOCK(spba_clk, 0, MX35_CCM_CGR2, 8, get_rate_ipg, NULL);
379 DEFINE_CLOCK(spdif_clk, 0, MX35_CCM_CGR2, 10, NULL, NULL);
380 DEFINE_CLOCK(ssi1_clk, 0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL);
381 DEFINE_CLOCK(ssi2_clk, 1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL);
382 DEFINE_CLOCK(uart1_clk, 0, MX35_CCM_CGR2, 16, get_rate_uart, NULL);
383 DEFINE_CLOCK(uart2_clk, 1, MX35_CCM_CGR2, 18, get_rate_uart, NULL);
384 DEFINE_CLOCK(uart3_clk, 2, MX35_CCM_CGR2, 20, get_rate_uart, NULL);
385 DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL);
386 DEFINE_CLOCK(wdog_clk, 0, MX35_CCM_CGR2, 24, NULL, NULL);
387 DEFINE_CLOCK(max_clk, 0, MX35_CCM_CGR2, 26, NULL, NULL);
388 DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL);
390 DEFINE_CLOCK(csi_clk, 0, MX35_CCM_CGR3, 0, get_rate_csi, NULL);
391 DEFINE_CLOCK(iim_clk, 0, MX35_CCM_CGR3, 2, NULL, NULL);
392 DEFINE_CLOCK(gpu2d_clk, 0, MX35_CCM_CGR3, 4, NULL, NULL);
394 DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
396 static int clk_dummy_enable(struct clk *clk)
401 static void clk_dummy_disable(struct clk *clk)
405 static unsigned long get_rate_nfc(struct clk *clk)
409 div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1;
411 return get_rate_ahb(NULL) / div1;
414 /* NAND Controller: It seems it can't be disabled */
415 static struct clk nfc_clk = {
419 .get_rate = get_rate_nfc,
420 .set_rate = NULL, /* set_rate_nfc, */
421 .enable = clk_dummy_enable,
422 .disable = clk_dummy_disable
425 #define _REGISTER_CLOCK(d, n, c) \
432 static struct clk_lookup lookups[] = {
433 _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
434 _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
435 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
436 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
437 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
438 _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
439 _REGISTER_CLOCK(NULL, "ect", ect_clk)
440 _REGISTER_CLOCK(NULL, "edio", edio_clk)
441 _REGISTER_CLOCK(NULL, "emi", emi_clk)
442 _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
443 _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
444 _REGISTER_CLOCK(NULL, "esai", esai_clk)
445 _REGISTER_CLOCK("sdhci-esdhc-imx35.0", NULL, esdhc1_clk)
446 _REGISTER_CLOCK("sdhci-esdhc-imx35.1", NULL, esdhc2_clk)
447 _REGISTER_CLOCK("sdhci-esdhc-imx35.2", NULL, esdhc3_clk)
448 /* i.mx35 has the i.mx27 type fec */
449 _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
450 _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
451 _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
452 _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
453 _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
454 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
455 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
456 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
457 _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
458 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
459 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
460 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
461 _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
462 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
463 _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
464 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
465 _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
466 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
467 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
468 _REGISTER_CLOCK(NULL, "scc", scc_clk)
469 _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
470 _REGISTER_CLOCK(NULL, "spba", spba_clk)
471 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
472 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
473 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
474 /* i.mx35 has the i.mx21 type uart */
475 _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
476 _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
477 _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
478 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
479 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
480 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
481 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
482 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
483 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
484 _REGISTER_CLOCK(NULL, "max", max_clk)
485 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
486 _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
487 _REGISTER_CLOCK(NULL, "iim", iim_clk)
488 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
489 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
492 int __init mx35_clocks_init()
494 unsigned int cgr2 = 3 << 26;
496 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
500 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
502 /* Turn off all clocks except the ones we need to survive, namely:
503 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
505 __raw_writel((3 << 18), MX35_CCM_CGR0);
506 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
508 __raw_writel(cgr2, MX35_CCM_CGR2);
509 __raw_writel(0, MX35_CCM_CGR3);
511 clk_enable(&iim_clk);
512 imx_print_silicon_rev("i.MX35", mx35_revision());
513 clk_disable(&iim_clk);
516 * Check if we came up in internal boot mode. If yes, we need some
517 * extra clocks turned on, otherwise the MX35 boot ROM code will
518 * hang after a watchdog reset.
520 if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) {
521 /* Additionally turn on UART1, SCC, and IIM clocks */
522 clk_enable(&iim_clk);
523 clk_enable(&uart1_clk);
524 clk_enable(&scc_clk);
527 #ifdef CONFIG_MXC_USE_EPIT
528 epit_timer_init(&epit1_clk,
529 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
531 mxc_timer_init(&gpt_clk,
532 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);