2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/cpu.h>
16 #include <linux/export.h>
17 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/pm_opp.h>
26 #include <linux/phy.h>
27 #include <linux/reboot.h>
28 #include <linux/regmap.h>
29 #include <linux/micrel_phy.h>
30 #include <linux/mfd/syscon.h>
31 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/system_misc.h>
40 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
41 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
43 if (IS_BUILTIN(CONFIG_PHYLIB)) {
44 /* min rx data delay */
45 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
46 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
47 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
49 /* max rx/tx clock delay, min rx/tx control delay */
50 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
51 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
52 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
53 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
54 MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
60 static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
62 phy_write(dev, 0x0d, device);
63 phy_write(dev, 0x0e, reg);
64 phy_write(dev, 0x0d, (1 << 14) | device);
65 phy_write(dev, 0x0e, val);
68 static int ksz9031rn_phy_fixup(struct phy_device *dev)
71 * min rx data delay, max rx/tx clock delay,
72 * min rx/tx control delay
74 mmd_write_reg(dev, 2, 4, 0);
75 mmd_write_reg(dev, 2, 5, 0);
76 mmd_write_reg(dev, 2, 8, 0x003ff);
81 static int ar8031_phy_fixup(struct phy_device *dev)
85 /* To enable AR8031 output a 125MHz clk from CLK_25M */
86 phy_write(dev, 0xd, 0x7);
87 phy_write(dev, 0xe, 0x8016);
88 phy_write(dev, 0xd, 0x4007);
90 val = phy_read(dev, 0xe);
93 phy_write(dev, 0xe, val);
95 /* introduce tx clock delay */
96 phy_write(dev, 0x1d, 0x5);
97 val = phy_read(dev, 0x1e);
99 phy_write(dev, 0x1e, val);
104 #define PHY_ID_AR8031 0x004dd074
106 static void __init imx6q_enet_phy_init(void)
108 if (IS_BUILTIN(CONFIG_PHYLIB)) {
109 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
110 ksz9021rn_phy_fixup);
111 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
112 ksz9031rn_phy_fixup);
113 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
118 static void __init imx6q_1588_init(void)
122 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
124 regmap_update_bits(gpr, IOMUXC_GPR1,
125 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
126 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
128 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
132 static void __init imx6q_init_machine(void)
134 struct device *parent;
136 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
137 imx_get_soc_revision());
139 mxc_arch_reset_init_dt();
141 parent = imx_soc_device_init();
143 pr_warn("failed to initialize soc device\n");
145 imx6q_enet_phy_init();
147 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
154 #define OCOTP_CFG3 0x440
155 #define OCOTP_CFG3_SPEED_SHIFT 16
156 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
158 static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
160 struct device_node *np;
164 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
166 pr_warn("failed to find ocotp node\n");
170 base = of_iomap(np, 0);
172 pr_warn("failed to map ocotp\n");
176 val = readl_relaxed(base + OCOTP_CFG3);
177 val >>= OCOTP_CFG3_SPEED_SHIFT;
178 if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
179 if (dev_pm_opp_disable(cpu_dev, 1200000000))
180 pr_warn("failed to disable 1.2 GHz OPP\n");
186 static void __init imx6q_opp_init(void)
188 struct device_node *np;
189 struct device *cpu_dev = get_cpu_device(0);
192 pr_warn("failed to get cpu0 device\n");
195 np = of_node_get(cpu_dev->of_node);
197 pr_warn("failed to find cpu0 node\n");
201 if (of_init_opp_table(cpu_dev)) {
202 pr_warn("failed to init OPP table\n");
206 imx6q_opp_check_1p2ghz(cpu_dev);
212 static struct platform_device imx6q_cpufreq_pdev = {
213 .name = "imx6q-cpufreq",
216 static void __init imx6q_init_late(void)
219 * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
220 * to run cpuidle on them.
222 if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
223 imx6q_cpuidle_init();
225 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
227 platform_device_register(&imx6q_cpufreq_pdev);
231 static void __init imx6q_map_io(void)
237 static void __init imx6q_init_irq(void)
239 imx_init_revision_from_anatop();
246 static const char *imx6q_dt_compat[] __initdata = {
252 DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
253 .smp = smp_ops(imx_smp_ops),
254 .map_io = imx6q_map_io,
255 .init_irq = imx6q_init_irq,
256 .init_machine = imx6q_init_machine,
257 .init_late = imx6q_init_late,
258 .dt_compat = imx6q_dt_compat,
259 .restart = mxc_restart,