2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_device.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/map.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
24 #include <mach/common.h>
25 #include <mach/hardware.h>
26 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/time.h>
29 #include <asm/mach/map.h>
30 #include <mach/gpio.h>
31 #include <mach/iomux-mx27.h>
33 #include "devices-imx27.h"
36 * Base address of PBC controller, CS4
38 #define PBC_BASE_ADDRESS 0xf4300000
39 #define PBC_REG_ADDR(offset) (void __force __iomem *) \
40 (PBC_BASE_ADDRESS + (offset))
42 /* When the PBC address connection is fixed in h/w, defined as 1 */
45 /* Offsets for the PBC Controller register */
47 * PBC Board version register offset
49 #define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
51 * PBC Board control register 1 set address.
53 #define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
55 * PBC Board control register 1 clear address.
57 #define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
59 /* PBC Board Control Register 1 bit definitions */
60 #define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
62 /* to determine the correct external crystal reference */
63 #define CKIH_27MHZ_BIT_SET (1 << 3)
65 static const int mx27ads_pins[] __initconst = {
108 PD11_AOUT_FEC_TX_CLK,
111 PD14_AOUT_FEC_RX_CLK,
164 static const struct mxc_nand_platform_data
165 mx27ads_nand_board_info __initconst = {
170 /* ADS's NOR flash */
171 static struct physmap_flash_data mx27ads_flash_data = {
175 static struct resource mx27ads_flash_resource = {
177 .end = 0xc0000000 + 0x02000000 - 1,
178 .flags = IORESOURCE_MEM,
182 static struct platform_device mx27ads_nor_mtd_device = {
183 .name = "physmap-flash",
186 .platform_data = &mx27ads_flash_data,
189 .resource = &mx27ads_flash_resource,
192 static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
196 static struct i2c_board_info mx27ads_i2c_devices[] = {
199 void lcd_power(int on)
202 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
204 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
207 static struct imx_fb_videomode mx27ads_modes[] = {
210 .name = "Sharp-LQ035Q7",
214 .pixclock = 188679, /* in ps (5.3MHz) */
227 static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
228 .mode = mx27ads_modes,
229 .num_modes = ARRAY_SIZE(mx27ads_modes),
232 * - HSYNC active high
233 * - VSYNC active high
234 * - clk notenabled while idle
236 * - data not inverted
237 * - data enable low active
238 * - enable sharp mode
244 .lcd_power = lcd_power,
247 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
250 return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
251 "sdhc1-card-detect", data);
254 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
257 return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
258 "sdhc2-card-detect", data);
261 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
263 free_irq(IRQ_GPIOE(21), data);
266 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
268 free_irq(IRQ_GPIOB(7), data);
271 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
272 .init = mx27ads_sdhc1_init,
273 .exit = mx27ads_sdhc1_exit,
276 static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
277 .init = mx27ads_sdhc2_init,
278 .exit = mx27ads_sdhc2_exit,
281 static struct platform_device *platform_devices[] __initdata = {
282 &mx27ads_nor_mtd_device,
285 static const struct imxuart_platform_data uart_pdata __initconst = {
286 .flags = IMXUART_HAVE_RTSCTS,
289 static void __init mx27ads_board_init(void)
293 mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
296 imx27_add_imx_uart0(&uart_pdata);
297 imx27_add_imx_uart1(&uart_pdata);
298 imx27_add_imx_uart2(&uart_pdata);
299 imx27_add_imx_uart3(&uart_pdata);
300 imx27_add_imx_uart4(&uart_pdata);
301 imx27_add_imx_uart5(&uart_pdata);
302 imx27_add_mxc_nand(&mx27ads_nand_board_info);
304 /* only the i2c master 1 is used on this CPU card */
305 i2c_register_board_info(1, mx27ads_i2c_devices,
306 ARRAY_SIZE(mx27ads_i2c_devices));
307 imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
308 imx27_add_imx_fb(&mx27ads_fb_data);
309 imx27_add_mxc_mmc(0, &sdhc1_pdata);
310 imx27_add_mxc_mmc(1, &sdhc2_pdata);
313 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
314 imx27_add_mxc_w1(NULL);
317 static void __init mx27ads_timer_init(void)
319 unsigned long fref = 26000000;
321 if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
324 mx27_clocks_init(fref);
327 static struct sys_timer mx27ads_timer = {
328 .init = mx27ads_timer_init,
331 static struct map_desc mx27ads_io_desc[] __initdata = {
333 .virtual = PBC_BASE_ADDRESS,
334 .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
340 static void __init mx27ads_map_io(void)
343 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
346 MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
347 /* maintainer: Freescale Semiconductor, Inc. */
348 .boot_params = MX27_PHYS_OFFSET + 0x100,
349 .map_io = mx27ads_map_io,
350 .init_early = imx27_init_early,
351 .init_irq = mx27_init_irq,
352 .timer = &mx27ads_timer,
353 .init_machine = mx27ads_board_init,