2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
16 #include <linux/of_address.h>
17 #include <linux/smp.h>
18 #include <asm/smp_plat.h>
21 #define SRC_GPR1 0x020
22 #define BP_SRC_SCR_WARM_RESET_ENABLE 0
23 #define BP_SRC_SCR_CORE1_RST 14
24 #define BP_SRC_SCR_CORE1_ENABLE 22
26 static void __iomem *src_base;
28 void imx_enable_cpu(int cpu, bool enable)
32 cpu = cpu_logical_map(cpu);
33 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
34 val = readl_relaxed(src_base + SRC_SCR);
35 val = enable ? val | mask : val & ~mask;
36 writel_relaxed(val, src_base + SRC_SCR);
39 void imx_set_cpu_jump(int cpu, void *jump_addr)
41 cpu = cpu_logical_map(cpu);
42 writel_relaxed(virt_to_phys(jump_addr),
43 src_base + SRC_GPR1 + cpu * 8);
46 u32 imx_get_cpu_arg(int cpu)
48 cpu = cpu_logical_map(cpu);
49 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
52 void imx_set_cpu_arg(int cpu, u32 arg)
54 cpu = cpu_logical_map(cpu);
55 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
58 void imx_src_prepare_restart(void)
62 /* clear enable bits of secondary cores */
63 val = readl_relaxed(src_base + SRC_SCR);
64 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
65 writel_relaxed(val, src_base + SRC_SCR);
67 /* clear persistent entry register of primary core */
68 writel_relaxed(0, src_base + SRC_GPR1);
71 void __init imx_src_init(void)
73 struct device_node *np;
76 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
77 src_base = of_iomap(np, 0);
81 * force warm reset sources to generate cold reset
82 * for a more reliable restart
84 val = readl_relaxed(src_base + SRC_SCR);
85 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
86 writel_relaxed(val, src_base + SRC_SCR);