arch/arm/mach-integrator/core.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/core.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/memblock.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/termios.h>
  21 #include <linux/amba/bus.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/io.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/platform.h>
  28 #include <mach/cm.h>
  29 #include <mach/irqs.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/leds.h>
  33 #include <asm/mach-types.h>
  34 #include <asm/mach/time.h>
  35 #include <asm/pgtable.h>
  36
  37 static struct amba_pl010_data integrator_uart_data;
  38
  39 #define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
  40 #define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
  41 #define INTEGRATOR_UART1_IRQ    { IRQ_UARTINT1 }
  42 #define KMI0_IRQ                { IRQ_KMIINT0 }
  43 #define KMI1_IRQ                { IRQ_KMIINT1 }
  44
  45 static AMBA_APB_DEVICE(rtc, "mb:15", 0,
  46         INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
  47
  48 static AMBA_APB_DEVICE(uart0, "mb:16", 0,
  49         INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
  50
  51 static AMBA_APB_DEVICE(uart1, "mb:17", 0,
  52         INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
  53
  54 static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
  55 static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
  56
  57 static struct amba_device *amba_devs[] __initdata = {
  58         &rtc_device,
  59         &uart0_device,
  60         &uart1_device,
  61         &kmi0_device,
  62         &kmi1_device,
  63 };
  64
  65 /*
  66  * These are fixed clocks.
  67  */
  68 static struct clk clk24mhz = {
  69         .rate   = 24000000,
  70 };
  71
  72 static struct clk uartclk = {
  73         .rate   = 14745600,
  74 };
  75
  76 static struct clk dummy_apb_pclk;
  77
  78 static struct clk_lookup lookups[] = {
  79         {       /* Bus clock */
  80                 .con_id         = "apb_pclk",
  81                 .clk            = &dummy_apb_pclk,
  82         }, {
  83                 /* Integrator/AP timer frequency */
  84                 .dev_id         = "ap_timer",
  85                 .clk            = &clk24mhz,
  86         }, {    /* UART0 */
  87                 .dev_id         = "mb:16",
  88                 .clk            = &uartclk,
  89         }, {    /* UART1 */
  90                 .dev_id         = "mb:17",
  91                 .clk            = &uartclk,
  92         }, {    /* KMI0 */
  93                 .dev_id         = "mb:18",
  94                 .clk            = &clk24mhz,
  95         }, {    /* KMI1 */
  96                 .dev_id         = "mb:19",
  97                 .clk            = &clk24mhz,
  98         }, {    /* MMCI - IntegratorCP */
  99                 .dev_id         = "mb:1c",
 100                 .clk            = &uartclk,
 101         }
 102 };
 103
 104 void __init integrator_init_early(void)
 105 {
 106         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 107 }
 108
 109 static int __init integrator_init(void)
 110 {
 111         int i;
 112
 113         /*
 114          * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
 115          * hard-code them. The Integator/CP and forward have proper cell IDs.
 116          * Else we leave them undefined to the bus driver can autoprobe them.
 117          */
 118         if (machine_is_integrator()) {
 119                 rtc_device.periphid     = 0x00041030;
 120                 uart0_device.periphid   = 0x00041010;
 121                 uart1_device.periphid   = 0x00041010;
 122                 kmi0_device.periphid    = 0x00041050;
 123                 kmi1_device.periphid    = 0x00041050;
 124         }
 125
 126         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 127                 struct amba_device *d = amba_devs[i];
 128                 amba_device_register(d, &iomem_resource);
 129         }
 130
 131         return 0;
 132 }
 133
 134 arch_initcall(integrator_init);
 135
 136 /*
 137  * On the Integrator platform, the port RTS and DTR are provided by
 138  * bits in the following SC_CTRLS register bits:
 139  *        RTS  DTR
 140  *  UART0  7    6
 141  *  UART1  5    4
 142  */
 143 #define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
 144 #define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
 145
 146 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 147 {
 148         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 149
 150         if (dev == &uart0_device) {
 151                 rts_mask = 1 << 4;
 152                 dtr_mask = 1 << 5;
 153         } else {
 154                 rts_mask = 1 << 6;
 155                 dtr_mask = 1 << 7;
 156         }
 157
 158         if (mctrl & TIOCM_RTS)
 159                 ctrlc |= rts_mask;
 160         else
 161                 ctrls |= rts_mask;
 162
 163         if (mctrl & TIOCM_DTR)
 164                 ctrlc |= dtr_mask;
 165         else
 166                 ctrls |= dtr_mask;
 167
 168         __raw_writel(ctrls, SC_CTRLS);
 169         __raw_writel(ctrlc, SC_CTRLC);
 170 }
 171
 172 static struct amba_pl010_data integrator_uart_data = {
 173         .set_mctrl = integrator_uart_set_mctrl,
 174 };
 175
 176 #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 177
 178 static DEFINE_RAW_SPINLOCK(cm_lock);
 179
 180 /**
 181  * cm_control - update the CM_CTRL register.
 182  * @mask: bits to change
 183  * @set: bits to set
 184  */
 185 void cm_control(u32 mask, u32 set)
 186 {
 187         unsigned long flags;
 188         u32 val;
 189
 190         raw_spin_lock_irqsave(&cm_lock, flags);
 191         val = readl(CM_CTRL) & ~mask;
 192         writel(val | set, CM_CTRL);
 193         raw_spin_unlock_irqrestore(&cm_lock, flags);
 194 }
 195
 196 EXPORT_SYMBOL(cm_control);
 197
 198 /*
 199  * We need to stop things allocating the low memory; ideally we need a
 200  * better implementation of GFP_DMA which does not assume that DMA-able
 201  * memory starts at zero.
 202  */
 203 void __init integrator_reserve(void)
 204 {
 205         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 206 }
 207
 208 /*
 209  * To reset, we hit the on-board reset register in the system FPGA
 210  */
 211 void integrator_restart(char mode, const char *cmd)
 212 {
 213         cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 214 }