arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/syscore_ops.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34 #include <linux/mtd/physmap.h>
  35 #include <linux/clk.h>
  36
  37 #include <mach/hardware.h>
  38 #include <mach/platform.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/irq.h>
  41 #include <asm/setup.h>
  42 #include <asm/param.h>          /* HZ */
  43 #include <asm/mach-types.h>
  44
  45 #include <mach/lm.h>
  46
  47 #include <asm/mach/arch.h>
  48 #include <asm/mach/irq.h>
  49 #include <asm/mach/map.h>
  50 #include <asm/mach/time.h>
  51
  52 #include <plat/fpga-irq.h>
  53
  54 #include "common.h"
  55
  56 /*
  57  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  58  * is the (PA >> 12).
  59  *
  60  * Setup a VA for the Integrator interrupt controller (for header #0,
  61  * just for now).
  62  */
  63 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  64 #define VA_SC_BASE      __io_address(INTEGRATOR_SC_BASE)
  65 #define VA_EBI_BASE     __io_address(INTEGRATOR_EBI_BASE)
  66 #define VA_CMIC_BASE    __io_address(INTEGRATOR_HDR_IC)
  67
  68 /*
  69  * Logical      Physical
  70  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  71  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  72  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  73  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  74  * ef000000                     Cache flush
  75  * f1000000     10000000        Core module registers
  76  * f1100000     11000000        System controller registers
  77  * f1200000     12000000        EBI registers
  78  * f1300000     13000000        Counter/Timer
  79  * f1400000     14000000        Interrupt controller
  80  * f1600000     16000000        UART 0
  81  * f1700000     17000000        UART 1
  82  * f1a00000     1a000000        Debug LEDs
  83  * f1b00000     1b000000        GPIO
  84  */
  85
  86 static struct map_desc ap_io_desc[] __initdata = {
  87         {
  88                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  89                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  90                 .length         = SZ_4K,
  91                 .type           = MT_DEVICE
  92         }, {
  93                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  94                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE
  97         }, {
  98                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  99                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 100                 .length         = SZ_4K,
 101                 .type           = MT_DEVICE
 102         }, {
 103                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 104                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE
 107         }, {
 108                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 109                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE
 112         }, {
 113                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 114                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 115                 .length         = SZ_4K,
 116                 .type           = MT_DEVICE
 117         }, {
 118                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 119                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE
 122         }, {
 123                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 124                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 125                 .length         = SZ_4K,
 126                 .type           = MT_DEVICE
 127         }, {
 128                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 129                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 130                 .length         = SZ_4K,
 131                 .type           = MT_DEVICE
 132         }, {
 133                 .virtual        = PCI_MEMORY_VADDR,
 134                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 135                 .length         = SZ_16M,
 136                 .type           = MT_DEVICE
 137         }, {
 138                 .virtual        = PCI_CONFIG_VADDR,
 139                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 140                 .length         = SZ_16M,
 141                 .type           = MT_DEVICE
 142         }, {
 143                 .virtual        = PCI_V3_VADDR,
 144                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 145                 .length         = SZ_64K,
 146                 .type           = MT_DEVICE
 147         }, {
 148                 .virtual        = PCI_IO_VADDR,
 149                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 150                 .length         = SZ_64K,
 151                 .type           = MT_DEVICE
 152         }
 153 };
 154
 155 static void __init ap_map_io(void)
 156 {
 157         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 158 }
 159
 160 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 161
 162 static struct fpga_irq_data sc_irq_data = {
 163         .base           = VA_IC_BASE,
 164         .irq_start      = 0,
 165         .chip.name      = "SC",
 166 };
 167
 168 static void __init ap_init_irq(void)
 169 {
 170         /* Disable all interrupts initially. */
 171         /* Do the core module ones */
 172         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 173
 174         /* do the header card stuff next */
 175         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 176         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 177
 178         fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
 179 }
 180
 181 #ifdef CONFIG_PM
 182 static unsigned long ic_irq_enable;
 183
 184 static int irq_suspend(void)
 185 {
 186         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 187         return 0;
 188 }
 189
 190 static void irq_resume(void)
 191 {
 192         /* disable all irq sources */
 193         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 194         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 195         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 196
 197         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 198 }
 199 #else
 200 #define irq_suspend NULL
 201 #define irq_resume NULL
 202 #endif
 203
 204 static struct syscore_ops irq_syscore_ops = {
 205         .suspend        = irq_suspend,
 206         .resume         = irq_resume,
 207 };
 208
 209 static int __init irq_syscore_init(void)
 210 {
 211         register_syscore_ops(&irq_syscore_ops);
 212
 213         return 0;
 214 }
 215
 216 device_initcall(irq_syscore_init);
 217
 218 /*
 219  * Flash handling.
 220  */
 221 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 222 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 223 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 224 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 225
 226 static int ap_flash_init(struct platform_device *dev)
 227 {
 228         u32 tmp;
 229
 230         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 231
 232         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 233         writel(tmp, EBI_CSR1);
 234
 235         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 236                 writel(0xa05f, EBI_LOCK);
 237                 writel(tmp, EBI_CSR1);
 238                 writel(0, EBI_LOCK);
 239         }
 240         return 0;
 241 }
 242
 243 static void ap_flash_exit(struct platform_device *dev)
 244 {
 245         u32 tmp;
 246
 247         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 248
 249         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 250         writel(tmp, EBI_CSR1);
 251
 252         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 253                 writel(0xa05f, EBI_LOCK);
 254                 writel(tmp, EBI_CSR1);
 255                 writel(0, EBI_LOCK);
 256         }
 257 }
 258
 259 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
 260 {
 261         void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
 262
 263         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 264 }
 265
 266 static struct physmap_flash_data ap_flash_data = {
 267         .width          = 4,
 268         .init           = ap_flash_init,
 269         .exit           = ap_flash_exit,
 270         .set_vpp        = ap_flash_set_vpp,
 271 };
 272
 273 static struct resource cfi_flash_resource = {
 274         .start          = INTEGRATOR_FLASH_BASE,
 275         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 276         .flags          = IORESOURCE_MEM,
 277 };
 278
 279 static struct platform_device cfi_flash_device = {
 280         .name           = "physmap-flash",
 281         .id             = 0,
 282         .dev            = {
 283                 .platform_data  = &ap_flash_data,
 284         },
 285         .num_resources  = 1,
 286         .resource       = &cfi_flash_resource,
 287 };
 288
 289 static void __init ap_init(void)
 290 {
 291         unsigned long sc_dec;
 292         int i;
 293
 294         platform_device_register(&cfi_flash_device);
 295
 296         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 297         for (i = 0; i < 4; i++) {
 298                 struct lm_device *lmdev;
 299
 300                 if ((sc_dec & (16 << i)) == 0)
 301                         continue;
 302
 303                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 304                 if (!lmdev)
 305                         continue;
 306
 307                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 308                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 309                 lmdev->resource.flags = IORESOURCE_MEM;
 310                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 311                 lmdev->id = i;
 312
 313                 lm_device_register(lmdev);
 314         }
 315 }
 316
 317 /*
 318  * Where is the timer (VA)?
 319  */
 320 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 321 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 322 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 323
 324 static unsigned long timer_reload;
 325
 326 static void integrator_clocksource_init(unsigned long inrate)
 327 {
 328         void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
 329         u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
 330         unsigned long rate = inrate;
 331
 332         if (rate >= 1500000) {
 333                 rate /= 16;
 334                 ctrl |= TIMER_CTRL_DIV16;
 335         }
 336
 337         writel(0xffff, base + TIMER_LOAD);
 338         writel(ctrl, base + TIMER_CTRL);
 339
 340         clocksource_mmio_init(base + TIMER_VALUE, "timer2",
 341                         rate, 200, 16, clocksource_mmio_readl_down);
 342 }
 343
 344 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
 345
 346 /*
 347  * IRQ handler for the timer
 348  */
 349 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 350 {
 351         struct clock_event_device *evt = dev_id;
 352
 353         /* clear the interrupt */
 354         writel(1, clkevt_base + TIMER_INTCLR);
 355
 356         evt->event_handler(evt);
 357
 358         return IRQ_HANDLED;
 359 }
 360
 361 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 362 {
 363         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 364
 365         /* Disable timer */
 366         writel(ctrl, clkevt_base + TIMER_CTRL);
 367
 368         switch (mode) {
 369         case CLOCK_EVT_MODE_PERIODIC:
 370                 /* Enable the timer and start the periodic tick */
 371                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 372                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 373                 writel(ctrl, clkevt_base + TIMER_CTRL);
 374                 break;
 375         case CLOCK_EVT_MODE_ONESHOT:
 376                 /* Leave the timer disabled, .set_next_event will enable it */
 377                 ctrl &= ~TIMER_CTRL_PERIODIC;
 378                 writel(ctrl, clkevt_base + TIMER_CTRL);
 379                 break;
 380         case CLOCK_EVT_MODE_UNUSED:
 381         case CLOCK_EVT_MODE_SHUTDOWN:
 382         case CLOCK_EVT_MODE_RESUME:
 383         default:
 384                 /* Just leave in disabled state */
 385                 break;
 386         }
 387
 388 }
 389
 390 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 391 {
 392         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 393
 394         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 395         writel(next, clkevt_base + TIMER_LOAD);
 396         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 397
 398         return 0;
 399 }
 400
 401 static struct clock_event_device integrator_clockevent = {
 402         .name           = "timer1",
 403         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 404         .set_mode       = clkevt_set_mode,
 405         .set_next_event = clkevt_set_next_event,
 406         .rating         = 300,
 407 };
 408
 409 static struct irqaction integrator_timer_irq = {
 410         .name           = "timer",
 411         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 412         .handler        = integrator_timer_interrupt,
 413         .dev_id         = &integrator_clockevent,
 414 };
 415
 416 static void integrator_clockevent_init(unsigned long inrate)
 417 {
 418         unsigned long rate = inrate;
 419         unsigned int ctrl = 0;
 420
 421         /* Calculate and program a divisor */
 422         if (rate > 0x100000 * HZ) {
 423                 rate /= 256;
 424                 ctrl |= TIMER_CTRL_DIV256;
 425         } else if (rate > 0x10000 * HZ) {
 426                 rate /= 16;
 427                 ctrl |= TIMER_CTRL_DIV16;
 428         }
 429         timer_reload = rate / HZ;
 430         writel(ctrl, clkevt_base + TIMER_CTRL);
 431
 432         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 433         clockevents_config_and_register(&integrator_clockevent,
 434                                         rate,
 435                                         1,
 436                                         0xffffU);
 437 }
 438
 439 /*
 440  * Set up timer(s).
 441  */
 442 static void __init ap_init_timer(void)
 443 {
 444         struct clk *clk;
 445         unsigned long rate;
 446
 447         clk = clk_get_sys("ap_timer", NULL);
 448         BUG_ON(IS_ERR(clk));
 449         clk_enable(clk);
 450         rate = clk_get_rate(clk);
 451
 452         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 453         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 454         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 455
 456         integrator_clocksource_init(rate);
 457         integrator_clockevent_init(rate);
 458 }
 459
 460 static struct sys_timer ap_timer = {
 461         .init           = ap_init_timer,
 462 };
 463
 464 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 465         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 466         .atag_offset    = 0x100,
 467         .reserve        = integrator_reserve,
 468         .map_io         = ap_map_io,
 469         .init_early     = integrator_init_early,
 470         .init_irq       = ap_init_irq,
 471         .timer          = &ap_timer,
 472         .init_machine   = ap_init,
 473 MACHINE_END