2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
34 #include <linux/mtd/physmap.h>
35 #include <linux/clk.h>
36 #include <linux/platform_data/clk-integrator.h>
37 #include <linux/of_irq.h>
38 #include <linux/of_address.h>
39 #include <linux/of_platform.h>
40 #include <video/vga.h>
42 #include <mach/hardware.h>
43 #include <mach/platform.h>
44 #include <asm/hardware/arm_timer.h>
45 #include <asm/setup.h>
46 #include <asm/param.h> /* HZ */
47 #include <asm/mach-types.h>
48 #include <asm/sched_clock.h>
51 #include <mach/irqs.h>
53 #include <asm/mach/arch.h>
54 #include <asm/mach/irq.h>
55 #include <asm/mach/map.h>
56 #include <asm/mach/pci.h>
57 #include <asm/mach/time.h>
59 #include <plat/fpga-irq.h>
64 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
67 * Setup a VA for the Integrator interrupt controller (for header #0,
70 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
71 #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
72 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
73 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
77 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
78 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
79 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
80 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
81 * ef000000 Cache flush
82 * f1000000 10000000 Core module registers
83 * f1100000 11000000 System controller registers
84 * f1200000 12000000 EBI registers
85 * f1300000 13000000 Counter/Timer
86 * f1400000 14000000 Interrupt controller
87 * f1600000 16000000 UART 0
88 * f1700000 17000000 UART 1
89 * f1a00000 1a000000 Debug LEDs
90 * f1b00000 1b000000 GPIO
93 static struct map_desc ap_io_desc[] __initdata = {
95 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
96 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
100 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
101 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
105 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
106 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
110 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
111 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
115 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
116 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
120 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
121 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
125 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
126 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
130 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
131 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
135 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
136 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
140 .virtual = (unsigned long)PCI_MEMORY_VADDR,
141 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
145 .virtual = (unsigned long)PCI_CONFIG_VADDR,
146 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
150 .virtual = (unsigned long)PCI_V3_VADDR,
151 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
157 static void __init ap_map_io(void)
159 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
160 vga_base = (unsigned long)PCI_MEMORY_VADDR;
161 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
165 static unsigned long ic_irq_enable;
167 static int irq_suspend(void)
169 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
173 static void irq_resume(void)
175 /* disable all irq sources */
176 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
177 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
178 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
180 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
183 #define irq_suspend NULL
184 #define irq_resume NULL
187 static struct syscore_ops irq_syscore_ops = {
188 .suspend = irq_suspend,
189 .resume = irq_resume,
192 static int __init irq_syscore_init(void)
194 register_syscore_ops(&irq_syscore_ops);
199 device_initcall(irq_syscore_init);
204 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
205 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
206 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
207 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
209 static int ap_flash_init(struct platform_device *dev)
213 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
215 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
216 writel(tmp, EBI_CSR1);
218 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
219 writel(0xa05f, EBI_LOCK);
220 writel(tmp, EBI_CSR1);
226 static void ap_flash_exit(struct platform_device *dev)
230 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
232 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
233 writel(tmp, EBI_CSR1);
235 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
236 writel(0xa05f, EBI_LOCK);
237 writel(tmp, EBI_CSR1);
242 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
244 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
246 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
249 static struct physmap_flash_data ap_flash_data = {
251 .init = ap_flash_init,
252 .exit = ap_flash_exit,
253 .set_vpp = ap_flash_set_vpp,
257 * Where is the timer (VA)?
259 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
260 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
261 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
263 static unsigned long timer_reload;
265 static u32 notrace integrator_read_sched_clock(void)
267 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
270 static void integrator_clocksource_init(unsigned long inrate,
273 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
274 unsigned long rate = inrate;
276 if (rate >= 1500000) {
278 ctrl |= TIMER_CTRL_DIV16;
281 writel(0xffff, base + TIMER_LOAD);
282 writel(ctrl, base + TIMER_CTRL);
284 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
285 rate, 200, 16, clocksource_mmio_readl_down);
286 setup_sched_clock(integrator_read_sched_clock, 16, rate);
289 static void __iomem * clkevt_base;
292 * IRQ handler for the timer
294 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
296 struct clock_event_device *evt = dev_id;
298 /* clear the interrupt */
299 writel(1, clkevt_base + TIMER_INTCLR);
301 evt->event_handler(evt);
306 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
308 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
311 writel(ctrl, clkevt_base + TIMER_CTRL);
314 case CLOCK_EVT_MODE_PERIODIC:
315 /* Enable the timer and start the periodic tick */
316 writel(timer_reload, clkevt_base + TIMER_LOAD);
317 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
318 writel(ctrl, clkevt_base + TIMER_CTRL);
320 case CLOCK_EVT_MODE_ONESHOT:
321 /* Leave the timer disabled, .set_next_event will enable it */
322 ctrl &= ~TIMER_CTRL_PERIODIC;
323 writel(ctrl, clkevt_base + TIMER_CTRL);
325 case CLOCK_EVT_MODE_UNUSED:
326 case CLOCK_EVT_MODE_SHUTDOWN:
327 case CLOCK_EVT_MODE_RESUME:
329 /* Just leave in disabled state */
335 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
337 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
339 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
340 writel(next, clkevt_base + TIMER_LOAD);
341 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
346 static struct clock_event_device integrator_clockevent = {
348 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
349 .set_mode = clkevt_set_mode,
350 .set_next_event = clkevt_set_next_event,
354 static struct irqaction integrator_timer_irq = {
356 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
357 .handler = integrator_timer_interrupt,
358 .dev_id = &integrator_clockevent,
361 static void integrator_clockevent_init(unsigned long inrate,
362 void __iomem *base, int irq)
364 unsigned long rate = inrate;
365 unsigned int ctrl = 0;
368 /* Calculate and program a divisor */
369 if (rate > 0x100000 * HZ) {
371 ctrl |= TIMER_CTRL_DIV256;
372 } else if (rate > 0x10000 * HZ) {
374 ctrl |= TIMER_CTRL_DIV16;
376 timer_reload = rate / HZ;
377 writel(ctrl, clkevt_base + TIMER_CTRL);
379 setup_irq(irq, &integrator_timer_irq);
380 clockevents_config_and_register(&integrator_clockevent,
386 void __init ap_init_early(void)
392 static void __init ap_init_timer_of(void)
394 struct device_node *node;
402 clk = clk_get_sys("ap_timer", NULL);
404 clk_prepare_enable(clk);
405 rate = clk_get_rate(clk);
407 err = of_property_read_string(of_aliases,
408 "arm,timer-primary", &path);
411 node = of_find_node_by_path(path);
412 base = of_iomap(node, 0);
415 writel(0, base + TIMER_CTRL);
416 integrator_clocksource_init(rate, base);
418 err = of_property_read_string(of_aliases,
419 "arm,timer-secondary", &path);
422 node = of_find_node_by_path(path);
423 base = of_iomap(node, 0);
426 irq = irq_of_parse_and_map(node, 0);
427 writel(0, base + TIMER_CTRL);
428 integrator_clockevent_init(rate, base, irq);
431 static struct sys_timer ap_of_timer = {
432 .init = ap_init_timer_of,
435 static const struct of_device_id fpga_irq_of_match[] __initconst = {
436 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
440 static void __init ap_init_irq_of(void)
442 /* disable core module IRQs */
443 writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
444 of_irq_init(fpga_irq_of_match);
445 integrator_clk_init(false);
448 /* For the Device Tree, add in the UART callbacks as AUXDATA */
449 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
450 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
452 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
453 "uart0", &integrator_uart_data),
454 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
455 "uart1", &integrator_uart_data),
456 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
458 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
460 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
461 "physmap-flash", &ap_flash_data),
465 static void __init ap_init_of(void)
467 unsigned long sc_dec;
470 of_platform_populate(NULL, of_default_bus_match_table,
471 ap_auxdata_lookup, NULL);
473 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
474 for (i = 0; i < 4; i++) {
475 struct lm_device *lmdev;
477 if ((sc_dec & (16 << i)) == 0)
480 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
484 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
485 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
486 lmdev->resource.flags = IORESOURCE_MEM;
487 lmdev->irq = IRQ_AP_EXPINT0 + i;
490 lm_device_register(lmdev);
494 static const char * ap_dt_board_compat[] = {
499 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
500 .reserve = integrator_reserve,
502 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
503 .init_early = ap_init_early,
504 .init_irq = ap_init_irq_of,
505 .handle_irq = fpga_handle_irq,
506 .timer = &ap_of_timer,
507 .init_machine = ap_init_of,
508 .restart = integrator_restart,
509 .dt_compat = ap_dt_board_compat,
517 * This is where non-devicetree initialization code is collected and stashed
518 * for eventual deletion.
521 static struct resource cfi_flash_resource = {
522 .start = INTEGRATOR_FLASH_BASE,
523 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
524 .flags = IORESOURCE_MEM,
527 static struct platform_device cfi_flash_device = {
528 .name = "physmap-flash",
531 .platform_data = &ap_flash_data,
534 .resource = &cfi_flash_resource,
537 static void __init ap_init_timer(void)
542 clk = clk_get_sys("ap_timer", NULL);
544 clk_prepare_enable(clk);
545 rate = clk_get_rate(clk);
547 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
548 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
549 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
551 integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
552 integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
556 static struct sys_timer ap_timer = {
557 .init = ap_init_timer,
560 #define INTEGRATOR_SC_VALID_INT 0x003fffff
562 static void __init ap_init_irq(void)
564 /* Disable all interrupts initially. */
565 /* Do the core module ones */
566 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
568 /* do the header card stuff next */
569 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
570 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
572 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
573 -1, INTEGRATOR_SC_VALID_INT, NULL);
574 integrator_clk_init(false);
577 static void __init ap_init(void)
579 unsigned long sc_dec;
582 platform_device_register(&cfi_flash_device);
584 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
585 for (i = 0; i < 4; i++) {
586 struct lm_device *lmdev;
588 if ((sc_dec & (16 << i)) == 0)
591 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
595 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
596 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
597 lmdev->resource.flags = IORESOURCE_MEM;
598 lmdev->irq = IRQ_AP_EXPINT0 + i;
601 lm_device_register(lmdev);
604 integrator_init(false);
607 MACHINE_START(INTEGRATOR, "ARM-Integrator")
608 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
609 .atag_offset = 0x100,
610 .reserve = integrator_reserve,
612 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
613 .init_early = ap_init_early,
614 .init_irq = ap_init_irq,
615 .handle_irq = fpga_handle_irq,
617 .init_machine = ap_init,
618 .restart = integrator_restart,