2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/sysdev.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/amba/mmci.h>
23 #include <linux/gfp.h>
25 #include <asm/clkdev.h>
26 #include <mach/clkdev.h>
27 #include <mach/hardware.h>
28 #include <mach/platform.h>
30 #include <asm/setup.h>
31 #include <asm/mach-types.h>
32 #include <asm/hardware/arm_timer.h>
33 #include <asm/hardware/icst.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/flash.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/time.h>
44 #include <plat/timer-sp.h>
48 #define INTCP_PA_FLASH_BASE 0x24000000
49 #define INTCP_FLASH_SIZE SZ_32M
51 #define INTCP_PA_CLCD_BASE 0xc0000000
53 #define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE + 0x40)
54 #define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
55 #define INTCP_VA_SIC_BASE IO_ADDRESS(INTEGRATOR_CP_SIC_BASE)
57 #define INTCP_ETH_SIZE 0x10
59 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
60 #define INTCP_FLASHPROG 0x04
61 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
62 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
66 * f1000000 10000000 Core module registers
67 * f1100000 11000000 System controller registers
68 * f1200000 12000000 EBI registers
69 * f1300000 13000000 Counter/Timer
70 * f1400000 14000000 Interrupt controller
71 * f1600000 16000000 UART 0
72 * f1700000 17000000 UART 1
73 * f1a00000 1a000000 Debug LEDs
74 * fc900000 c9000000 GPIO
75 * fca00000 ca000000 SIC
76 * fcb00000 cb000000 CP system control
79 static struct map_desc intcp_io_desc[] __initdata = {
81 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
82 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
86 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
87 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
91 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
92 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
96 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
97 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
101 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
102 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
106 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
107 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
111 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
112 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
116 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
117 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
121 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
122 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
126 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
127 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
131 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
132 .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
138 static void __init intcp_map_io(void)
140 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
143 #define cic_writel __raw_writel
144 #define cic_readl __raw_readl
145 #define pic_writel __raw_writel
146 #define pic_readl __raw_readl
147 #define sic_writel __raw_writel
148 #define sic_readl __raw_readl
150 static void cic_mask_irq(unsigned int irq)
152 irq -= IRQ_CIC_START;
153 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
156 static void cic_unmask_irq(unsigned int irq)
158 irq -= IRQ_CIC_START;
159 cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
162 static struct irq_chip cic_chip = {
165 .mask = cic_mask_irq,
166 .unmask = cic_unmask_irq,
169 static void pic_mask_irq(unsigned int irq)
171 irq -= IRQ_PIC_START;
172 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
175 static void pic_unmask_irq(unsigned int irq)
177 irq -= IRQ_PIC_START;
178 pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
181 static struct irq_chip pic_chip = {
184 .mask = pic_mask_irq,
185 .unmask = pic_unmask_irq,
188 static void sic_mask_irq(unsigned int irq)
190 irq -= IRQ_SIC_START;
191 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
194 static void sic_unmask_irq(unsigned int irq)
196 irq -= IRQ_SIC_START;
197 sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
200 static struct irq_chip sic_chip = {
203 .mask = sic_mask_irq,
204 .unmask = sic_unmask_irq,
208 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
210 unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
213 do_bad_IRQ(irq, desc);
218 irq = ffs(status) - 1;
219 status &= ~(1 << irq);
221 irq += IRQ_SIC_START;
223 generic_handle_irq(irq);
227 static void __init intcp_init_irq(void)
232 * Disable all interrupt sources
234 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
235 pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
237 for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
242 set_irq_chip(i, &pic_chip);
243 set_irq_handler(i, handle_level_irq);
244 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
247 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
248 cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
250 for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
251 set_irq_chip(i, &cic_chip);
252 set_irq_handler(i, handle_level_irq);
253 set_irq_flags(i, IRQF_VALID);
256 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
257 sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
259 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
260 set_irq_chip(i, &sic_chip);
261 set_irq_handler(i, handle_level_irq);
262 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
265 set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
271 #define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
272 #define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
274 static const struct icst_params cp_auxvco_params = {
276 .vco_max = ICST525_VCO_MAX_5V,
277 .vco_min = ICST525_VCO_MIN,
282 .s2div = icst525_s2div,
283 .idx2s = icst525_idx2s,
286 static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
290 val = readl(clk->vcoreg) & ~0x7ffff;
291 val |= vco.v | (vco.r << 9) | (vco.s << 16);
293 writel(0xa05f, CM_LOCK);
294 writel(val, clk->vcoreg);
298 static const struct clk_ops cp_auxclk_ops = {
299 .round = icst_clk_round,
301 .setvco = cp_auxvco_set,
304 static struct clk cp_auxclk = {
305 .ops = &cp_auxclk_ops,
306 .params = &cp_auxvco_params,
310 static struct clk_lookup cp_lookups[] = {
320 static int intcp_flash_init(void)
324 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
325 val |= CINTEGRATOR_FLASHPROG_FLWREN;
326 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
331 static void intcp_flash_exit(void)
335 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
336 val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
337 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
340 static void intcp_flash_set_vpp(int on)
344 val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
346 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
348 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
349 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
352 static struct flash_platform_data intcp_flash_data = {
353 .map_name = "cfi_probe",
355 .init = intcp_flash_init,
356 .exit = intcp_flash_exit,
357 .set_vpp = intcp_flash_set_vpp,
360 static struct resource intcp_flash_resource = {
361 .start = INTCP_PA_FLASH_BASE,
362 .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
363 .flags = IORESOURCE_MEM,
366 static struct platform_device intcp_flash_device = {
370 .platform_data = &intcp_flash_data,
373 .resource = &intcp_flash_resource,
376 static struct resource smc91x_resources[] = {
378 .start = INTEGRATOR_CP_ETH_BASE,
379 .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
380 .flags = IORESOURCE_MEM,
383 .start = IRQ_CP_ETHINT,
384 .end = IRQ_CP_ETHINT,
385 .flags = IORESOURCE_IRQ,
389 static struct platform_device smc91x_device = {
392 .num_resources = ARRAY_SIZE(smc91x_resources),
393 .resource = smc91x_resources,
396 static struct platform_device *intcp_devs[] __initdata = {
402 * It seems that the card insertion interrupt remains active after
403 * we've acknowledged it. We therefore ignore the interrupt, and
404 * rely on reading it from the SIC. This also means that we must
405 * clear the latched interrupt.
407 static unsigned int mmc_status(struct device *dev)
409 unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
410 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
415 static struct mmci_platform_data mmc_data = {
416 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
417 .status = mmc_status,
422 static struct amba_device mmc_device = {
424 .init_name = "mb:1c",
425 .platform_data = &mmc_data,
428 .start = INTEGRATOR_CP_MMC_BASE,
429 .end = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
430 .flags = IORESOURCE_MEM,
432 .irq = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
436 static struct amba_device aaci_device = {
438 .init_name = "mb:1d",
441 .start = INTEGRATOR_CP_AACI_BASE,
442 .end = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
443 .flags = IORESOURCE_MEM,
445 .irq = { IRQ_CP_AACIINT, NO_IRQ },
453 static struct clcd_panel vga = {
467 .vmode = FB_VMODE_NONINTERLACED,
471 .tim2 = TIM2_BCD | TIM2_IPC,
472 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
478 * Ensure VGA is selected.
480 static void cp_clcd_enable(struct clcd_fb *fb)
484 if (fb->fb.var.bits_per_pixel <= 8)
485 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
486 else if (fb->fb.var.bits_per_pixel <= 16)
487 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
488 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
489 | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
491 val = 0; /* no idea for this, don't trust the docs */
493 cm_control(CM_CTRL_LCDMUXSEL_MASK|
499 CM_CTRL_n24BITEN, val);
502 static unsigned long framesize = SZ_1M;
504 static int cp_clcd_setup(struct clcd_fb *fb)
510 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
512 if (!fb->fb.screen_base) {
513 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
517 fb->fb.fix.smem_start = dma;
518 fb->fb.fix.smem_len = framesize;
523 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
525 return dma_mmap_writecombine(&fb->dev->dev, vma,
527 fb->fb.fix.smem_start,
528 fb->fb.fix.smem_len);
531 static void cp_clcd_remove(struct clcd_fb *fb)
533 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
534 fb->fb.screen_base, fb->fb.fix.smem_start);
537 static struct clcd_board clcd_data = {
538 .name = "Integrator/CP",
539 .check = clcdfb_check,
540 .decode = clcdfb_decode,
541 .enable = cp_clcd_enable,
542 .setup = cp_clcd_setup,
543 .mmap = cp_clcd_mmap,
544 .remove = cp_clcd_remove,
547 static struct amba_device clcd_device = {
549 .init_name = "mb:c0",
550 .coherent_dma_mask = ~0,
551 .platform_data = &clcd_data,
554 .start = INTCP_PA_CLCD_BASE,
555 .end = INTCP_PA_CLCD_BASE + SZ_4K - 1,
556 .flags = IORESOURCE_MEM,
559 .irq = { IRQ_CP_CLCDCINT, NO_IRQ },
563 static struct amba_device *amba_devs[] __initdata = {
569 static void __init intcp_init(void)
573 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
574 platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
576 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
577 struct amba_device *d = amba_devs[i];
578 amba_device_register(d, &iomem_resource);
582 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
583 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
584 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
586 static void __init intcp_timer_init(void)
588 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
589 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
590 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
592 sp804_clocksource_init(TIMER2_VA_BASE);
593 sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
596 static struct sys_timer cp_timer = {
597 .init = intcp_timer_init,
600 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
601 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
602 .boot_params = 0x00000100,
603 .map_io = intcp_map_io,
604 .reserve = integrator_reserve,
605 .init_irq = intcp_init_irq,
607 .init_machine = intcp_init,