2 * linux/arch/arm/mach-integrator/pci_v3.c
4 * PCI functions for V3 host PCI bridge
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/ioport.h>
27 #include <linux/interrupt.h>
28 #include <linux/spinlock.h>
29 #include <linux/init.h>
31 #include <asm/hardware.h>
34 #include <asm/system.h>
35 #include <asm/mach/pci.h>
37 #include <asm/hardware/pci_v3.h>
40 * The V3 PCI interface chip in Integrator provides several windows from
41 * local bus memory into the PCI memory areas. Unfortunately, there
42 * are not really enough windows for our usage, therefore we reuse
43 * one of the windows for access to PCI configuration space. The
44 * memory map is as follows:
46 * Local Bus Memory Usage
48 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
49 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
50 * 60000000 - 60FFFFFF PCI IO. 16M
51 * 61000000 - 61FFFFFF PCI Configuration. 16M
53 * There are three V3 windows, each described by a pair of V3 registers.
54 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
55 * Base0 and Base1 can be used for any type of PCI memory access. Base2
56 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
57 * uses this only for PCI IO space.
59 * Normally these spaces are mapped using the following base registers:
61 * Usage Local Bus Memory Base/Map registers used
63 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
64 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
65 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
66 * Cfg 61000000 - 61FFFFFF
68 * This means that I20 and PCI configuration space accesses will fail.
69 * When PCI configuration accesses are needed (via the uHAL PCI
70 * configuration space primitives) we must remap the spaces as follows:
72 * Usage Local Bus Memory Base/Map registers used
74 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
75 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
76 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
77 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
79 * To make this work, the code depends on overlapping windows working.
80 * The V3 chip translates an address by checking its range within
81 * each of the BASE/MAP pairs in turn (in ascending register number
82 * order). It will use the first matching pair. So, for example,
83 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
84 * LB_BASE1/LB_MAP1, the V3 will use the translation from
87 * To allow PCI Configuration space access, the code enlarges the
88 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
89 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
90 * be remapped for use by configuration cycles.
92 * At the end of the PCI Configuration space accesses,
93 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
94 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
95 * reveal the now restored LB_BASE1/LB_MAP1 window.
97 * NOTE: We do not set up I2O mapping. I suspect that this is only
98 * for an intelligent (target) device. Using I2O disables most of
99 * the mappings into PCI memory.
102 // V3 access routines
103 #define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
104 #define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
106 #define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
107 #define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
109 #define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
110 #define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
112 /*============================================================================
114 * routine: uHALir_PCIMakeConfigAddress()
116 * parameters: bus = which bus
117 * device = which device
118 * function = which function
119 * offset = configuration space register we are interested in
121 * description: this routine will generate a platform dependent config
126 * returns: configuration address to play on the PCI bus
128 * To generate the appropriate PCI configuration cycles in the PCI
129 * configuration address space, you present the V3 with the following pattern
130 * (which is very nearly a type 1 (except that the lower two bits are 00 and
131 * not 01). In order for this mapping to work you need to set up one of
132 * the local to PCI aperatures to 16Mbytes in length translating to
133 * PCI configuration space starting at 0x0000.0000.
135 * PCI configuration cycles look like this:
139 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
140 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
141 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
142 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
143 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
145 * 31:11 Device select bit.
146 * 10:8 Function number
147 * 7:2 Register number
151 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
152 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
153 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
154 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
155 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
158 * 23:16 bus number (8 bits = 128 possible buses)
159 * 15:11 Device number (5 bits)
160 * 10:8 function number
161 * 7:2 register number
164 static DEFINE_SPINLOCK(v3_lock);
166 #define PCI_BUS_NONMEM_START 0x00000000
167 #define PCI_BUS_NONMEM_SIZE SZ_256M
169 #define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
170 #define PCI_BUS_PREMEM_SIZE SZ_256M
172 #if PCI_BUS_NONMEM_START & 0x000fffff
173 #error PCI_BUS_NONMEM_START must be megabyte aligned
175 #if PCI_BUS_PREMEM_START & 0x000fffff
176 #error PCI_BUS_PREMEM_START must be megabyte aligned
179 #undef V3_LB_BASE_PREFETCH
180 #define V3_LB_BASE_PREFETCH 0
182 static unsigned long v3_open_config_window(struct pci_bus *bus,
183 unsigned int devfn, int offset)
185 unsigned int address, mapaddress, busnr;
190 * Trap out illegal values
200 int slot = PCI_SLOT(devfn);
203 * local bus segment so need a type 0 config cycle
205 * build the PCI configuration "address" with one-hot in
209 * 3:1 = config cycle (101)
210 * 0 = PCI A1 & A0 are 0 (0)
212 address = PCI_FUNC(devfn) << 8;
213 mapaddress = V3_LB_MAP_TYPE_CONFIG;
217 * high order bits are handled by the MAP register
219 mapaddress |= 1 << (slot - 5);
222 * low order bits handled directly in the address
224 address |= 1 << (slot + 11);
227 * not the local bus segment so need a type 1 config cycle
231 * 15:11 = slot number (7:3 of devfn)
232 * 10:8 = func number (2:0 of devfn)
235 * 3:1 = config cycle (101)
236 * 0 = PCI A1 & A0 from host bus (1)
238 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
239 address = (busnr << 16) | (devfn << 8);
243 * Set up base0 to see all 512Mbytes of memory space (not
244 * prefetchable), this frees up base1 for re-use by
245 * configuration memory
247 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
248 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
251 * Set up base1/map1 to point into configuration space.
253 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
254 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
255 v3_writew(V3_LB_MAP1, mapaddress);
257 return PCI_CONFIG_VADDR + address + offset;
260 static void v3_close_config_window(void)
263 * Reassign base1 for use by prefetchable PCI memory
265 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
266 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
268 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
269 V3_LB_MAP_TYPE_MEM_MULTIPLE);
272 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
274 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
275 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
278 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
285 spin_lock_irqsave(&v3_lock, flags);
286 addr = v3_open_config_window(bus, devfn, where);
290 v = __raw_readb(addr);
294 v = __raw_readw(addr);
298 v = __raw_readl(addr);
302 v3_close_config_window();
303 spin_unlock_irqrestore(&v3_lock, flags);
306 return PCIBIOS_SUCCESSFUL;
309 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
315 spin_lock_irqsave(&v3_lock, flags);
316 addr = v3_open_config_window(bus, devfn, where);
320 __raw_writeb((u8)val, addr);
325 __raw_writew((u16)val, addr);
330 __raw_writel(val, addr);
335 v3_close_config_window();
336 spin_unlock_irqrestore(&v3_lock, flags);
338 return PCIBIOS_SUCCESSFUL;
341 static struct pci_ops pci_v3_ops = {
342 .read = v3_read_config,
343 .write = v3_write_config,
346 static struct resource non_mem = {
347 .name = "PCI non-prefetchable",
348 .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
349 .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
350 .flags = IORESOURCE_MEM,
353 static struct resource pre_mem = {
354 .name = "PCI prefetchable",
355 .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
356 .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
357 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
360 static int __init pci_v3_setup_resources(struct resource **resource)
362 if (request_resource(&iomem_resource, &non_mem)) {
363 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
367 if (request_resource(&iomem_resource, &pre_mem)) {
368 release_resource(&non_mem);
369 printk(KERN_ERR "PCI: unable to allocate prefetchable "
375 * bus->resource[0] is the IO resource for this bus
376 * bus->resource[1] is the mem resource for this bus
377 * bus->resource[2] is the prefetch mem resource for this bus
379 resource[0] = &ioport_resource;
380 resource[1] = &non_mem;
381 resource[2] = &pre_mem;
387 * These don't seem to be implemented on the Integrator I have, which
388 * means I can't get additional information on the reason for the pm2fb
389 * problems. I suppose I'll just have to mind-meld with the machine. ;)
391 #define SC_PCI (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_PCIENABLE_OFFSET)
392 #define SC_LBFADDR (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x20)
393 #define SC_LBFCODE (IO_ADDRESS(INTEGRATOR_SC_BASE) + 0x24)
396 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
398 unsigned long pc = instruction_pointer(regs);
399 unsigned long instr = *(unsigned long *)pc;
403 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
404 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
405 v3_readb(V3_LB_ISTAT));
406 printk(KERN_DEBUG "%s", buf);
410 v3_writeb(V3_LB_ISTAT, 0);
411 __raw_writel(3, SC_PCI);
414 * If the instruction being executed was a read,
415 * make it look like it read all-ones.
417 if ((instr & 0x0c100000) == 0x04100000) {
418 int reg = (instr >> 12) & 15;
421 if (instr & 0x00400000)
426 regs->uregs[reg] = val;
431 if ((instr & 0x0e100090) == 0x00100090) {
432 int reg = (instr >> 12) & 15;
434 regs->uregs[reg] = -1;
442 static irqreturn_t v3_irq(int irq, void *devid)
444 #ifdef CONFIG_DEBUG_LL
445 struct pt_regs *regs = get_irq_regs();
446 unsigned long pc = instruction_pointer(regs);
447 unsigned long instr = *(unsigned long *)pc;
450 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", irq,
451 pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
452 v3_readb(V3_LB_ISTAT));
456 v3_writew(V3_PCI_STAT, 0xf000);
457 v3_writeb(V3_LB_ISTAT, 0);
458 __raw_writel(3, SC_PCI);
460 #ifdef CONFIG_DEBUG_LL
462 * If the instruction being executed was a read,
463 * make it look like it read all-ones.
465 if ((instr & 0x0c100000) == 0x04100000) {
466 int reg = (instr >> 16) & 15;
467 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
474 int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
479 sys->mem_offset = PHYS_PCI_MEM_BASE;
480 ret = pci_v3_setup_resources(sys->resource);
486 struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
488 return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
492 * V3_LB_BASE? - local bus address
493 * V3_LB_MAP? - pci bus address
495 void __init pci_v3_preinit(void)
502 * Hook in our fault handler for PCI errors
504 hook_fault_code(4, v3_pci_fault, SIGBUS, "external abort on linefetch");
505 hook_fault_code(6, v3_pci_fault, SIGBUS, "external abort on linefetch");
506 hook_fault_code(8, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
507 hook_fault_code(10, v3_pci_fault, SIGBUS, "external abort on non-linefetch");
509 spin_lock_irqsave(&v3_lock, flags);
512 * Unlock V3 registers, but only if they were previously locked.
514 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
515 v3_writew(V3_SYSTEM, 0xa05f);
518 * Setup window 0 - PCI non-prefetchable memory
519 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
521 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
522 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
523 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
527 * Setup window 1 - PCI prefetchable memory
528 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
530 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
531 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
533 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
534 V3_LB_MAP_TYPE_MEM_MULTIPLE);
537 * Setup window 2 - PCI IO
539 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
541 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
544 * Disable PCI to host IO cycles
546 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
547 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
548 v3_writew(V3_PCI_CFG, temp);
550 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
551 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
554 * Set the V3 FIFO such that writes have higher priority than
555 * reads, and local bus write causes local bus read fifo flush.
558 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
561 * Re-lock the system register.
563 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
564 v3_writew(V3_SYSTEM, temp);
567 * Clear any error conditions, and enable write errors.
569 v3_writeb(V3_LB_ISTAT, 0);
570 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
571 v3_writeb(V3_LB_IMASK, 0x28);
572 __raw_writel(3, SC_PCI);
575 * Grab the PCI error interrupt.
577 ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
579 printk(KERN_ERR "PCI: unable to grab PCI error "
580 "interrupt: %d\n", ret);
582 spin_unlock_irqrestore(&v3_lock, flags);
585 void __init pci_v3_postinit(void)
587 unsigned int pci_cmd;
589 pci_cmd = PCI_COMMAND_MEMORY |
590 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
592 v3_writew(V3_PCI_CMD, pci_cmd);
594 v3_writeb(V3_LB_ISTAT, ~0x40);
595 v3_writeb(V3_LB_IMASK, 0x68);
598 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
600 printk(KERN_ERR "PCI: unable to grab local bus timeout "
601 "interrupt: %d\n", ret);
604 register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);