3 * Copyright (c) 2005-2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 #include <linux/pci.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/jiffies.h>
24 #include <linux/export.h>
26 #include <mach/hardware.h>
27 #include <asm/sizes.h>
28 #include <asm/signal.h>
29 #include <asm/mach/pci.h>
32 #define IOP13XX_PCI_DEBUG 0
33 #define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
35 u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
36 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
37 static struct pci_bus *pci_bus_atux = 0;
38 static struct pci_bus *pci_bus_atue = 0;
39 void __iomem *iop13xx_atue_mem_base;
40 void __iomem *iop13xx_atux_mem_base;
41 size_t iop13xx_atue_mem_size;
42 size_t iop13xx_atux_mem_size;
44 EXPORT_SYMBOL(iop13xx_atue_mem_base);
45 EXPORT_SYMBOL(iop13xx_atux_mem_base);
46 EXPORT_SYMBOL(iop13xx_atue_mem_size);
47 EXPORT_SYMBOL(iop13xx_atux_mem_size);
49 int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */
50 static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first
53 /* Scan the initialized busses and ioremap the requested memory range
55 void iop13xx_map_pci_memory(void)
60 resource_size_t end = 0;
62 for (atu = 0; atu < 2; atu++) {
63 bus = atu ? pci_bus_atue : pci_bus_atux;
65 list_for_each_entry(dev, &bus->devices, bus_list) {
70 max = DEVICE_COUNT_RESOURCE;
72 for (i = 0; i < max; i++) {
73 struct resource *res = &dev->resource[i];
74 if (res->flags & IORESOURCE_MEM)
75 end = max(res->end, end);
81 iop13xx_atux_mem_size =
82 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
84 /* 16MB align the request */
85 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
86 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
87 iop13xx_atux_mem_size += SZ_16M;
91 iop13xx_atux_mem_base = __arm_ioremap_pfn(
92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
93 , 0, iop13xx_atux_mem_size, MT_DEVICE);
94 if (!iop13xx_atux_mem_base) {
95 printk("%s: atux allocation "
96 "failed\n", __func__);
100 iop13xx_atux_mem_size = 0;
101 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
102 __func__, atu, iop13xx_atux_mem_size,
103 iop13xx_atux_mem_base);
106 iop13xx_atue_mem_size =
107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
109 /* 16MB align the request */
110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
111 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
112 iop13xx_atue_mem_size += SZ_16M;
116 iop13xx_atue_mem_base = __arm_ioremap_pfn(
117 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
118 , 0, iop13xx_atue_mem_size, MT_DEVICE);
119 if (!iop13xx_atue_mem_base) {
120 printk("%s: atue allocation "
121 "failed\n", __func__);
125 iop13xx_atue_mem_size = 0;
126 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
127 __func__, atu, iop13xx_atue_mem_size,
128 iop13xx_atue_mem_base);
132 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
133 atu ? "ATUE" : "ATUX",
134 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
136 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
137 IOP13XX_PCIX_LOWER_MEM_RA,
138 atu ? iop13xx_atue_mem_base :
139 iop13xx_atux_mem_base);
146 static int iop13xx_atu_function(int atu)
149 /* the function number depends on the value of the
150 * IOP13XX_INTERFACE_SEL_PCIX reset strap
151 * see C-Spec section 3.17
154 case IOP13XX_INIT_ATU_ATUX:
155 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
160 case IOP13XX_INIT_ATU_ATUE:
161 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
173 /* iop13xx_atux_cfg_address - format a configuration address for atux
174 * @bus: Target bus to access
175 * @devfn: Combined device number and function number
176 * @where: Desired register's address offset
178 * Convert the parameters to a configuration address formatted
179 * according the PCI-X 2.0 specification
181 static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
183 struct pci_sys_data *sys = bus->sysdata;
186 if (sys->busnr == bus->number)
187 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
189 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
191 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
192 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */
197 /* iop13xx_atue_cfg_address - format a configuration address for atue
198 * @bus: Target bus to access
199 * @devfn: Combined device number and function number
200 * @where: Desired register's address offset
202 * Convert the parameters to an address usable by the ATUE_OCCAR
204 static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
206 struct pci_sys_data *sys = bus->sysdata;
209 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
210 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
211 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
212 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
213 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
216 if (sys->busnr != bus->number)
217 addr |= 1; /* type 1 access */
222 /* This routine checks the status of the last configuration cycle. If an error
223 * was detected it returns >0, else it returns a 0. The errors being checked
224 * are parity, master abort, target abort (master and target). These types of
225 * errors occur during a config cycle where there is no device, like during
226 * the discovery stage.
228 static int iop13xx_atux_pci_status(int clear)
234 * Check the status registers.
236 status = __raw_readw(IOP13XX_ATUX_ATUSR);
237 if (status & IOP_PCI_STATUS_ERROR)
239 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
241 __raw_writew(status & IOP_PCI_STATUS_ERROR,
245 status = __raw_readl(IOP13XX_ATUX_ATUISR);
246 if (status & IOP13XX_ATUX_ATUISR_ERROR)
248 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
250 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
251 IOP13XX_ATUX_ATUISR);
257 /* Simply write the address register and read the configuration
258 * data. Note that the data dependency on %0 encourages an abort
259 * to be detected before we return.
261 static u32 iop13xx_atux_read(unsigned long addr)
265 __asm__ __volatile__(
270 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
275 /* The read routines must check the error status of the last configuration
276 * cycle. If there was an error, the routine returns all hex f's.
279 iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
280 int size, u32 *value)
282 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
283 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
285 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
293 return PCIBIOS_SUCCESSFUL;
297 iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
300 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
304 val = iop13xx_atux_read(addr);
305 if (!iop13xx_atux_pci_status(1) == 0)
306 return PCIBIOS_SUCCESSFUL;
308 where = (where & 3) * 8;
311 val &= ~(0xff << where);
313 val &= ~(0xffff << where);
315 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
317 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
318 __raw_writel(value, IOP13XX_ATUX_OCCDR);
321 return PCIBIOS_SUCCESSFUL;
324 static struct pci_ops iop13xx_atux_ops = {
325 .read = iop13xx_atux_read_config,
326 .write = iop13xx_atux_write_config,
329 /* This routine checks the status of the last configuration cycle. If an error
330 * was detected it returns >0, else it returns a 0. The errors being checked
331 * are parity, master abort, target abort (master and target). These types of
332 * errors occur during a config cycle where there is no device, like during
333 * the discovery stage.
335 static int iop13xx_atue_pci_status(int clear)
341 * Check the status registers.
344 /* standard pci status register */
345 status = __raw_readw(IOP13XX_ATUE_ATUSR);
346 if (status & IOP_PCI_STATUS_ERROR) {
347 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
349 __raw_writew(status & IOP_PCI_STATUS_ERROR,
354 /* check the normal status bits in the ATUISR */
355 status = __raw_readl(IOP13XX_ATUE_ATUISR);
356 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
357 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
359 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
360 IOP13XX_ATUE_ATUISR);
363 /* check the PCI-E status if the ATUISR reports an interface error */
364 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
365 /* get the unmasked errors */
366 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
367 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
370 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
371 __raw_readl(IOP13XX_ATUE_PIE_STS));
374 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
375 __raw_readl(IOP13XX_ATUE_PIE_STS));
376 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
377 __raw_readl(IOP13XX_ATUE_PIE_MSK));
382 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
390 iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
395 case 1: return ATUE_INTA;
396 case 2: return ATUE_INTB;
397 case 3: return ATUE_INTC;
398 case 4: return ATUE_INTD;
403 static u32 iop13xx_atue_read(unsigned long addr)
407 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
408 val = __raw_readl(IOP13XX_ATUE_OCCDR);
415 /* The read routines must check the error status of the last configuration
416 * cycle. If there was an error, the routine returns all hex f's.
419 iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
420 int size, u32 *value)
423 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
425 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */
426 if (!PCI_SLOT(devfn) || (addr & 1)) {
427 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
428 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
429 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
434 PRINTK("addr=%#0lx, val=%#010x", addr, val);
440 return PCIBIOS_SUCCESSFUL;
444 iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
447 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
451 val = iop13xx_atue_read(addr);
452 if (!iop13xx_atue_pci_status(1) == 0)
453 return PCIBIOS_SUCCESSFUL;
455 where = (where & 3) * 8;
458 val &= ~(0xff << where);
460 val &= ~(0xffff << where);
462 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
464 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
465 __raw_writel(value, IOP13XX_ATUE_OCCDR);
468 return PCIBIOS_SUCCESSFUL;
471 static struct pci_ops iop13xx_atue_ops = {
472 .read = iop13xx_atue_read_config,
473 .write = iop13xx_atue_write_config,
476 /* When a PCI device does not exist during config cycles, the XScale gets a
477 * bus error instead of returning 0xffffffff. We can't rely on the ATU status
478 * bits to tell us that it was indeed a configuration cycle that caused this
479 * error especially in the case when the ATUE link is down. Instead we rely
480 * on data from the south XSI bridge to validate the abort
483 iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
485 PRINTK("Data abort: address = 0x%08lx "
486 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
487 addr, fsr, regs->ARM_pc, regs->ARM_lr);
489 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
490 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
491 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
493 /* If it was an imprecise abort, then we need to correct the
494 * return address to be _after_ the instruction.
499 if (is_atue_occdr_error() || is_atux_occdr_error())
505 /* Scan an IOP13XX PCI bus. nr selects which ATU we use.
507 struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
510 struct pci_bus *bus = NULL;
513 case IOP13XX_INIT_ATU_ATUX:
514 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
516 case IOP13XX_INIT_ATU_ATUE:
517 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
519 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
520 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
532 case IOP13XX_INIT_ATU_ATUX:
533 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
534 atux_trhfa_timeout)) /* ensure not wrap */
535 while(time_before(jiffies, atux_trhfa_timeout))
538 bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr,
540 sys, &sys->resources);
542 case IOP13XX_INIT_ATU_ATUE:
543 bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr,
545 sys, &sys->resources);
552 /* This function is called from iop13xx_pci_init() after assigning valid
553 * values to iop13xx_atue_pmmr_offset. This is the location for common
554 * setup of ATUE for all IOP13XX implementations.
556 void __init iop13xx_atue_setup(void)
558 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
561 #ifdef CONFIG_PCI_MSI
562 /* BAR 0 (inbound msi window) */
563 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
564 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
565 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
566 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
569 /* BAR 1 (1:1 mapping with Physical RAM) */
570 /* Set limit and enable */
571 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
573 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
575 /* Set base at the top of the reserved address space */
576 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
577 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
579 /* 1:1 mapping with physical ram
580 * (leave big endian byte swap disabled)
582 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
583 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
585 /* Outbound window 1 (PCIX/PCIE memory window) */
586 /* 32 bit Address Space */
587 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
589 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
590 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
591 IOP13XX_ATUE_OUMBAR1);
596 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
597 IOP13XX_ATUE_OIOBAR);
598 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
600 /* clear startup errors */
601 iop13xx_atue_pci_status(1);
603 /* OIOBAR function number
605 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
608 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
610 /* OUMBAR function numbers
612 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
613 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
614 IOP13XX_ATU_OUMBAR_FUNC_NUM);
615 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
616 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
618 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
619 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
620 IOP13XX_ATU_OUMBAR_FUNC_NUM);
621 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
622 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
624 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
625 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
626 IOP13XX_ATU_OUMBAR_FUNC_NUM);
627 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
628 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
630 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
631 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
632 IOP13XX_ATU_OUMBAR_FUNC_NUM);
633 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
634 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
636 /* Enable inbound and outbound cycles
638 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
639 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
640 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
641 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
643 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
644 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
645 IOP13XX_ATUE_ATUCR_IVM;
646 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
649 void __init iop13xx_atue_disable(void)
653 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
654 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
656 /* wait for cycles to quiesce */
657 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
658 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
659 IOP13XX_ATUE_PCSR_LLRB_BUSY))
662 /* BAR 0 ( Disabled ) */
663 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
664 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
665 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
666 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
667 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
668 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
669 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
670 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
672 /* BAR 1 ( Disabled ) */
673 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
674 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
675 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
676 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
677 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
678 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
679 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
680 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
682 /* BAR 2 ( Disabled ) */
683 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
684 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
685 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
686 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
687 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
688 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
689 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
690 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
692 /* BAR 3 ( Disabled ) */
693 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
694 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
695 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
700 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
701 IOP13XX_ATUE_OIOBAR);
702 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
705 /* This function is called from iop13xx_pci_init() after assigning valid
706 * values to iop13xx_atux_pmmr_offset. This is the location for common
707 * setup of ATUX for all IOP13XX implementations.
709 void __init iop13xx_atux_setup(void)
712 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
714 /* Take PCI-X bus out of reset if bootloader hasn't already.
715 * According to spec, we should wait for 2^25 PCI clocks to meet
716 * the PCI timing parameter Trhfa (RST# high to first access).
717 * This is rarely necessary and often ignored.
719 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
720 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
721 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
722 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */
723 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
725 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
728 atux_trhfa_timeout = jiffies;
730 #ifdef CONFIG_PCI_MSI
731 /* BAR 0 (inbound msi window) */
732 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
733 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
734 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
735 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
738 /* BAR 1 (1:1 mapping with Physical RAM) */
739 /* Set limit and enable */
740 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
742 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
744 /* Set base at the top of the reserved address space */
745 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
746 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
748 /* 1:1 mapping with physical ram
749 * (leave big endian byte swap disabled)
751 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
752 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
754 /* Outbound window 1 (PCIX/PCIE memory window) */
755 /* 32 bit Address Space */
756 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
758 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
759 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
760 IOP13XX_ATUX_OUMBAR1);
765 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
766 IOP13XX_ATUX_OIOBAR);
767 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
769 /* clear startup errors */
770 iop13xx_atux_pci_status(1);
772 /* OIOBAR function number
774 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
777 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
779 /* OUMBAR function numbers
781 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
782 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
783 IOP13XX_ATU_OUMBAR_FUNC_NUM);
784 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
785 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
787 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
788 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
789 IOP13XX_ATU_OUMBAR_FUNC_NUM);
790 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
791 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
793 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
794 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
795 IOP13XX_ATU_OUMBAR_FUNC_NUM);
796 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
797 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
799 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
800 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
801 IOP13XX_ATU_OUMBAR_FUNC_NUM);
802 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
803 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
805 /* Enable inbound and outbound cycles
807 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
808 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
809 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
810 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
812 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
813 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
814 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
817 void __init iop13xx_atux_disable(void)
821 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
822 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
824 /* wait for cycles to quiesce */
825 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
826 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
829 /* BAR 0 ( Disabled ) */
830 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
831 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
832 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
833 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
834 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
835 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
836 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
837 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
839 /* BAR 1 ( Disabled ) */
840 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
841 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
842 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
843 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
844 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
845 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
846 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
847 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
849 /* BAR 2 ( Disabled ) */
850 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
851 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
852 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
853 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
854 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
855 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
856 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
857 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
859 /* BAR 3 ( Disabled ) */
860 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
861 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
862 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
863 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
864 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
865 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
866 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
867 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
872 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
873 IOP13XX_ATUX_OIOBAR);
874 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
877 void __init iop13xx_set_atu_mmr_bases(void)
879 /* Based on ESSR0, determine the ATU X/E offsets */
880 switch(__raw_readl(IOP13XX_ESSR0) &
881 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
884 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
885 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
887 /* IOP13XX_CONTROLLER_ONLY = deasserted
888 * IOP13XX_INTERFACE_SEL_PCIX = asserted
890 case IOP13XX_CONTROLLER_ONLY:
891 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
892 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
894 /* IOP13XX_CONTROLLER_ONLY = asserted
895 * IOP13XX_INTERFACE_SEL_PCIX = deasserted
897 case IOP13XX_INTERFACE_SEL_PCIX:
898 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
899 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
901 /* both deasserted */
902 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
903 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
904 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
911 void __init iop13xx_atu_select(struct hw_pci *plat_pci)
915 /* set system defaults
916 * note: if "iop13xx_init_atu=" is specified this autodetect
917 * sequence will be bypassed
919 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
920 /* check for single/dual interface */
921 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
922 /* ATUE must be present check the device id
923 * to see if ATUX is present.
925 init_atu |= IOP13XX_INIT_ATU_ATUE;
926 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
930 init_atu |= IOP13XX_INIT_ATU_ATUX;
934 /* ATUX must be present check the device id
935 * to see if ATUE is present.
937 init_atu |= IOP13XX_INIT_ATU_ATUX;
938 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
942 init_atu |= IOP13XX_INIT_ATU_ATUE;
947 /* check central resource and root complex capability */
948 if (init_atu & IOP13XX_INIT_ATU_ATUX)
949 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
950 IOP13XX_ATUX_PCSR_CENTRAL_RES))
951 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
953 if (init_atu & IOP13XX_INIT_ATU_ATUE)
954 if (__raw_readl(IOP13XX_ATUE_PCSR) &
955 IOP13XX_ATUE_PCSR_END_POINT)
956 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
959 for (i = 0; i < 2; i++) {
960 if((init_atu & (1 << i)) == (1 << i))
961 plat_pci->nr_controllers++;
965 void __init iop13xx_pci_init(void)
967 /* clear pre-existing south bridge errors */
968 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
970 /* Setup the Min Address for PCI memory... */
971 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
973 /* if Linux is given control of an ATU
974 * clear out its prior configuration,
975 * otherwise do not touch the registers
977 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
978 iop13xx_atue_disable();
979 iop13xx_atue_setup();
982 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
983 iop13xx_atux_disable();
984 iop13xx_atux_setup();
987 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
988 "imprecise external abort");
991 /* initialize the pci memory space. handle any combination of
992 * atue and atux enabled/disabled
994 int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
996 struct resource *res;
1003 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1005 panic("PCI: unable to alloc resources");
1008 /* 'nr' assumptions:
1010 * ATUE is 1 when ATUX is also enabled
1011 * ATUE is 0 when ATUX is disabled
1014 case IOP13XX_INIT_ATU_ATUX:
1015 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1017 case IOP13XX_INIT_ATU_ATUE:
1018 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1020 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1021 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1033 case IOP13XX_INIT_ATU_ATUX:
1034 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1036 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1037 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1038 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1039 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1040 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1042 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
1044 res->start = IOP13XX_PCIX_LOWER_MEM_RA;
1045 res->end = IOP13XX_PCIX_UPPER_MEM_RA;
1046 res->name = "IQ81340 ATUX PCI Memory Space";
1047 res->flags = IORESOURCE_MEM;
1048 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1050 case IOP13XX_INIT_ATU_ATUE:
1051 /* Note: the function number field in the PCSR is ro */
1052 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1053 pcsr &= ~(0xfff8 << 16);
1054 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1055 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1057 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1059 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
1061 res->start = IOP13XX_PCIE_LOWER_MEM_RA;
1062 res->end = IOP13XX_PCIE_UPPER_MEM_RA;
1063 res->name = "IQ81340 ATUE PCI Memory Space";
1064 res->flags = IORESOURCE_MEM;
1065 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1066 sys->map_irq = iop13xx_pcie_map_irq;
1073 request_resource(&iomem_resource, res);
1075 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
1080 u16 iop13xx_dev_id(void)
1082 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1083 return __raw_readw(IOP13XX_ATUE_DID);
1085 return __raw_readw(IOP13XX_ATUX_DID);
1088 static int __init iop13xx_init_atu_setup(char *str)
1090 init_atu = IOP13XX_INIT_ATU_NONE;
1092 while (*str != '\0') {
1096 init_atu |= IOP13XX_INIT_ATU_ATUX;
1097 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1101 init_atu |= IOP13XX_INIT_ATU_ATUE;
1102 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1108 PRINTK("\"iop13xx_init_atu\" malformed at "
1109 "character: \'%c\'", *str);
1111 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1119 __setup("iop13xx_init_atu", iop13xx_init_atu_setup);