2 * iop13xx platform Initialization
3 * Copyright (c) 2005-2006, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/serial_8250.h>
23 #ifdef CONFIG_MTD_PHYSMAP
24 #include <linux/mtd/physmap.h>
26 #include <asm/mach/map.h>
27 #include <mach/hardware.h>
29 #include <asm/hardware/iop_adma.h>
31 #define IOP13XX_UART_XTAL 33334000
32 #define IOP13XX_SETUP_DEBUG 0
33 #define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
35 /* Standard IO mapping for all IOP13XX based systems
37 static struct map_desc iop13xx_std_desc[] __initdata = {
38 { /* mem mapped registers */
39 .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
40 .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
41 .length = IOP13XX_PMMR_SIZE,
46 static struct resource iop13xx_uart0_resources[] = {
48 .start = IOP13XX_UART0_PHYS,
49 .end = IOP13XX_UART0_PHYS + 0x3f,
50 .flags = IORESOURCE_MEM,
53 .start = IRQ_IOP13XX_UART0,
54 .end = IRQ_IOP13XX_UART0,
55 .flags = IORESOURCE_IRQ
59 static struct resource iop13xx_uart1_resources[] = {
61 .start = IOP13XX_UART1_PHYS,
62 .end = IOP13XX_UART1_PHYS + 0x3f,
63 .flags = IORESOURCE_MEM,
66 .start = IRQ_IOP13XX_UART1,
67 .end = IRQ_IOP13XX_UART1,
68 .flags = IORESOURCE_IRQ
72 static struct plat_serial8250_port iop13xx_uart0_data[] = {
74 .membase = IOP13XX_UART0_VIRT,
75 .mapbase = IOP13XX_UART0_PHYS,
76 .irq = IRQ_IOP13XX_UART0,
77 .uartclk = IOP13XX_UART_XTAL,
80 .flags = UPF_SKIP_TEST,
85 static struct plat_serial8250_port iop13xx_uart1_data[] = {
87 .membase = IOP13XX_UART1_VIRT,
88 .mapbase = IOP13XX_UART1_PHYS,
89 .irq = IRQ_IOP13XX_UART1,
90 .uartclk = IOP13XX_UART_XTAL,
93 .flags = UPF_SKIP_TEST,
98 /* The ids are fixed up later in iop13xx_platform_init */
99 static struct platform_device iop13xx_uart0 = {
100 .name = "serial8250",
102 .dev.platform_data = iop13xx_uart0_data,
104 .resource = iop13xx_uart0_resources,
107 static struct platform_device iop13xx_uart1 = {
108 .name = "serial8250",
110 .dev.platform_data = iop13xx_uart1_data,
112 .resource = iop13xx_uart1_resources
115 static struct resource iop13xx_i2c_0_resources[] = {
117 .start = IOP13XX_I2C0_PHYS,
118 .end = IOP13XX_I2C0_PHYS + 0x18,
119 .flags = IORESOURCE_MEM,
122 .start = IRQ_IOP13XX_I2C_0,
123 .end = IRQ_IOP13XX_I2C_0,
124 .flags = IORESOURCE_IRQ
128 static struct resource iop13xx_i2c_1_resources[] = {
130 .start = IOP13XX_I2C1_PHYS,
131 .end = IOP13XX_I2C1_PHYS + 0x18,
132 .flags = IORESOURCE_MEM,
135 .start = IRQ_IOP13XX_I2C_1,
136 .end = IRQ_IOP13XX_I2C_1,
137 .flags = IORESOURCE_IRQ
141 static struct resource iop13xx_i2c_2_resources[] = {
143 .start = IOP13XX_I2C2_PHYS,
144 .end = IOP13XX_I2C2_PHYS + 0x18,
145 .flags = IORESOURCE_MEM,
148 .start = IRQ_IOP13XX_I2C_2,
149 .end = IRQ_IOP13XX_I2C_2,
150 .flags = IORESOURCE_IRQ
154 /* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
155 * we just use the same device name.
158 /* The ids are fixed up later in iop13xx_platform_init */
159 static struct platform_device iop13xx_i2c_0_controller = {
160 .name = "IOP3xx-I2C",
163 .resource = iop13xx_i2c_0_resources
166 static struct platform_device iop13xx_i2c_1_controller = {
167 .name = "IOP3xx-I2C",
170 .resource = iop13xx_i2c_1_resources
173 static struct platform_device iop13xx_i2c_2_controller = {
174 .name = "IOP3xx-I2C",
177 .resource = iop13xx_i2c_2_resources
180 #ifdef CONFIG_MTD_PHYSMAP
183 static struct physmap_flash_data iq8134x_flash_data = {
187 static struct resource iq8134x_flash_resource = {
188 .start = IQ81340_FLASHBASE,
190 .flags = IORESOURCE_MEM,
193 static struct platform_device iq8134x_flash = {
194 .name = "physmap-flash",
196 .dev = { .platform_data = &iq8134x_flash_data, },
198 .resource = &iq8134x_flash_resource,
201 static unsigned long iq8134x_probe_flash_size(void)
203 uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
206 unsigned long size = 0;
207 int width = iq8134x_flash_data.width;
210 /* send CFI 'query' command */
211 writew(0x98, flash_addr);
213 /* check for CFI compliance */
214 for (i = 0; i < 3 * width; i += width)
215 query[i / width] = readb(flash_addr + (0x10 * width) + i);
218 if (memcmp(query, "QRY", 3) == 0)
219 size = 1 << readb(flash_addr + (0x27 * width));
221 /* send CFI 'read array' command */
222 writew(0xff, flash_addr);
232 static struct resource iop13xx_adma_0_resources[] = {
234 .start = IOP13XX_ADMA_PHYS_BASE(0),
235 .end = IOP13XX_ADMA_UPPER_PA(0),
236 .flags = IORESOURCE_MEM,
239 .start = IRQ_IOP13XX_ADMA0_EOT,
240 .end = IRQ_IOP13XX_ADMA0_EOT,
241 .flags = IORESOURCE_IRQ
244 .start = IRQ_IOP13XX_ADMA0_EOC,
245 .end = IRQ_IOP13XX_ADMA0_EOC,
246 .flags = IORESOURCE_IRQ
249 .start = IRQ_IOP13XX_ADMA0_ERR,
250 .end = IRQ_IOP13XX_ADMA0_ERR,
251 .flags = IORESOURCE_IRQ
255 static struct resource iop13xx_adma_1_resources[] = {
257 .start = IOP13XX_ADMA_PHYS_BASE(1),
258 .end = IOP13XX_ADMA_UPPER_PA(1),
259 .flags = IORESOURCE_MEM,
262 .start = IRQ_IOP13XX_ADMA1_EOT,
263 .end = IRQ_IOP13XX_ADMA1_EOT,
264 .flags = IORESOURCE_IRQ
267 .start = IRQ_IOP13XX_ADMA1_EOC,
268 .end = IRQ_IOP13XX_ADMA1_EOC,
269 .flags = IORESOURCE_IRQ
272 .start = IRQ_IOP13XX_ADMA1_ERR,
273 .end = IRQ_IOP13XX_ADMA1_ERR,
274 .flags = IORESOURCE_IRQ
278 static struct resource iop13xx_adma_2_resources[] = {
280 .start = IOP13XX_ADMA_PHYS_BASE(2),
281 .end = IOP13XX_ADMA_UPPER_PA(2),
282 .flags = IORESOURCE_MEM,
285 .start = IRQ_IOP13XX_ADMA2_EOT,
286 .end = IRQ_IOP13XX_ADMA2_EOT,
287 .flags = IORESOURCE_IRQ
290 .start = IRQ_IOP13XX_ADMA2_EOC,
291 .end = IRQ_IOP13XX_ADMA2_EOC,
292 .flags = IORESOURCE_IRQ
295 .start = IRQ_IOP13XX_ADMA2_ERR,
296 .end = IRQ_IOP13XX_ADMA2_ERR,
297 .flags = IORESOURCE_IRQ
301 static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(64);
302 static struct iop_adma_platform_data iop13xx_adma_0_data = {
304 .pool_size = PAGE_SIZE,
307 static struct iop_adma_platform_data iop13xx_adma_1_data = {
309 .pool_size = PAGE_SIZE,
312 static struct iop_adma_platform_data iop13xx_adma_2_data = {
314 .pool_size = PAGE_SIZE,
317 /* The ids are fixed up later in iop13xx_platform_init */
318 static struct platform_device iop13xx_adma_0_channel = {
322 .resource = iop13xx_adma_0_resources,
324 .dma_mask = &iop13xx_adma_dmamask,
325 .coherent_dma_mask = DMA_BIT_MASK(64),
326 .platform_data = (void *) &iop13xx_adma_0_data,
330 static struct platform_device iop13xx_adma_1_channel = {
334 .resource = iop13xx_adma_1_resources,
336 .dma_mask = &iop13xx_adma_dmamask,
337 .coherent_dma_mask = DMA_BIT_MASK(64),
338 .platform_data = (void *) &iop13xx_adma_1_data,
342 static struct platform_device iop13xx_adma_2_channel = {
346 .resource = iop13xx_adma_2_resources,
348 .dma_mask = &iop13xx_adma_dmamask,
349 .coherent_dma_mask = DMA_BIT_MASK(64),
350 .platform_data = (void *) &iop13xx_adma_2_data,
354 void __init iop13xx_map_io(void)
356 /* Initialize the Static Page Table maps */
357 iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
360 static int init_uart;
362 static int init_adma;
364 void __init iop13xx_platform_init(void)
367 u32 uart_idx, i2c_idx, adma_idx, plat_idx;
368 struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
370 /* set the bases so we can read the device id */
371 iop13xx_set_atu_mmr_bases();
373 memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
375 if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
376 switch (iop13xx_dev_id()) {
377 /* enable both uarts on iop341 */
382 init_uart |= IOP13XX_INIT_UART_0;
383 init_uart |= IOP13XX_INIT_UART_1;
385 /* only enable uart 1 */
387 init_uart |= IOP13XX_INIT_UART_1;
391 if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
392 switch (iop13xx_dev_id()) {
393 /* enable all i2c units on iop341 and iop342 */
402 init_i2c |= IOP13XX_INIT_I2C_0;
403 init_i2c |= IOP13XX_INIT_I2C_1;
404 init_i2c |= IOP13XX_INIT_I2C_2;
406 /* only enable i2c 1 and 2 */
408 init_i2c |= IOP13XX_INIT_I2C_1;
409 init_i2c |= IOP13XX_INIT_I2C_2;
413 if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
414 init_adma |= IOP13XX_INIT_ADMA_0;
415 init_adma |= IOP13XX_INIT_ADMA_1;
416 init_adma |= IOP13XX_INIT_ADMA_2;
423 /* uart 1 (if enabled) is ttyS0 */
424 if (init_uart & IOP13XX_INIT_UART_1) {
425 PRINTK("Adding uart1 to platform device list\n");
426 iop13xx_uart1.id = uart_idx++;
427 iop13xx_devices[plat_idx++] = &iop13xx_uart1;
429 if (init_uart & IOP13XX_INIT_UART_0) {
430 PRINTK("Adding uart0 to platform device list\n");
431 iop13xx_uart0.id = uart_idx++;
432 iop13xx_devices[plat_idx++] = &iop13xx_uart0;
435 for(i = 0; i < IQ81340_NUM_I2C; i++) {
436 if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
437 printk("Adding i2c%d to platform device list\n", i);
438 switch(init_i2c & (1 << i)) {
439 case IOP13XX_INIT_I2C_0:
440 iop13xx_i2c_0_controller.id = i2c_idx++;
441 iop13xx_devices[plat_idx++] =
442 &iop13xx_i2c_0_controller;
444 case IOP13XX_INIT_I2C_1:
445 iop13xx_i2c_1_controller.id = i2c_idx++;
446 iop13xx_devices[plat_idx++] =
447 &iop13xx_i2c_1_controller;
449 case IOP13XX_INIT_I2C_2:
450 iop13xx_i2c_2_controller.id = i2c_idx++;
451 iop13xx_devices[plat_idx++] =
452 &iop13xx_i2c_2_controller;
457 /* initialize adma channel ids and capabilities */
459 for (i = 0; i < IQ81340_NUM_ADMA; i++) {
460 struct iop_adma_platform_data *plat_data;
461 if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
463 "Adding adma%d to platform device list\n", i);
464 switch (init_adma & (1 << i)) {
465 case IOP13XX_INIT_ADMA_0:
466 iop13xx_adma_0_channel.id = adma_idx++;
467 iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
468 plat_data = &iop13xx_adma_0_data;
469 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
470 dma_cap_set(DMA_XOR, plat_data->cap_mask);
471 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
472 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
474 case IOP13XX_INIT_ADMA_1:
475 iop13xx_adma_1_channel.id = adma_idx++;
476 iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
477 plat_data = &iop13xx_adma_1_data;
478 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
479 dma_cap_set(DMA_XOR, plat_data->cap_mask);
480 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
481 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
483 case IOP13XX_INIT_ADMA_2:
484 iop13xx_adma_2_channel.id = adma_idx++;
485 iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
486 plat_data = &iop13xx_adma_2_data;
487 dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
488 dma_cap_set(DMA_XOR, plat_data->cap_mask);
489 dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
490 dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
491 dma_cap_set(DMA_PQ, plat_data->cap_mask);
492 dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
497 #ifdef CONFIG_MTD_PHYSMAP
498 iq8134x_flash_resource.end = iq8134x_flash_resource.start +
499 iq8134x_probe_flash_size() - 1;
500 if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
501 iop13xx_devices[plat_idx++] = &iq8134x_flash;
503 printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
506 platform_add_devices(iop13xx_devices, plat_idx);
509 static int __init iop13xx_init_uart_setup(char *str)
512 while (*str != '\0') {
515 init_uart |= IOP13XX_INIT_UART_0;
518 init_uart |= IOP13XX_INIT_UART_1;
524 PRINTK("\"iop13xx_init_uart\" malformed"
525 " at character: \'%c\'", *str);
527 init_uart = IOP13XX_INIT_UART_DEFAULT;
535 static int __init iop13xx_init_i2c_setup(char *str)
538 while (*str != '\0') {
541 init_i2c |= IOP13XX_INIT_I2C_0;
544 init_i2c |= IOP13XX_INIT_I2C_1;
547 init_i2c |= IOP13XX_INIT_I2C_2;
553 PRINTK("\"iop13xx_init_i2c\" malformed"
554 " at character: \'%c\'", *str);
556 init_i2c = IOP13XX_INIT_I2C_DEFAULT;
564 static int __init iop13xx_init_adma_setup(char *str)
567 while (*str != '\0') {
570 init_adma |= IOP13XX_INIT_ADMA_0;
573 init_adma |= IOP13XX_INIT_ADMA_1;
576 init_adma |= IOP13XX_INIT_ADMA_2;
582 PRINTK("\"iop13xx_init_adma\" malformed"
583 " at character: \'%c\'", *str);
585 init_adma = IOP13XX_INIT_ADMA_DEFAULT;
593 __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
594 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
595 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
597 void iop13xx_restart(char mode, const char *cmd)
600 * Reset the internal bus (warning both cores are reset)
602 write_wdtcr(IOP_WDTCR_EN_ARM);
603 write_wdtcr(IOP_WDTCR_EN);
604 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);