2 * arch/arm/mach-ixp23xx/pci.c
4 * PCI routines for IXP23XX based systems
6 * Copyright (c) 2005 MontaVista Software, Inc.
8 * based on original code:
10 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
11 * Copyright 2002-2005 Intel Corp.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
30 #include <asm/sizes.h>
31 #include <asm/system.h>
32 #include <asm/mach/pci.h>
33 #include <mach/hardware.h>
35 extern int (*external_fault) (unsigned long, struct pt_regs *);
37 static volatile int pci_master_aborts = 0;
40 #define DBG(x...) printk(x)
45 int clear_master_aborts(void);
48 *ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
53 * Must be dword aligned
58 * For top bus, generate type 0, else type 1
61 if (PCI_SLOT(devfn) >= 8)
64 paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
65 | (1 << (PCI_SLOT(devfn) + 16))
66 | (PCI_FUNC(devfn) << 8) | where);
68 paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
70 | (PCI_SLOT(devfn) << 11)
71 | (PCI_FUNC(devfn) << 8) | where);
78 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
79 * 0 and 3 are not valid indexes...
81 static u32 bytemask[] = {
89 static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 *value)
97 DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
98 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
100 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
102 return PCIBIOS_DEVICE_NOT_FOUND;
104 pci_master_aborts = 0;
105 *value = (*addr >> (8*n)) & bytemask[size];
106 if (pci_master_aborts) {
107 pci_master_aborts = 0;
109 return PCIBIOS_DEVICE_NOT_FOUND;
112 return PCIBIOS_SUCCESSFUL;
116 * We don't do error checking on the address for writes.
117 * It's assumed that the user checked for the device existing first
118 * by doing a read first.
120 static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 value)
127 mask = ~(bytemask[size] << ((where % 0x4) * 8));
128 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
130 return PCIBIOS_DEVICE_NOT_FOUND;
131 temp = (u32) (value) << ((where % 0x4) * 8);
132 *addr = (*addr & mask) | temp;
134 clear_master_aborts();
136 return PCIBIOS_SUCCESSFUL;
139 struct pci_ops ixp23xx_pci_ops = {
140 .read = ixp23xx_pci_read_config,
141 .write = ixp23xx_pci_write_config,
144 struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
146 return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
149 int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
151 volatile unsigned long temp;
154 pci_master_aborts = 1;
156 local_irq_save(flags);
157 temp = *IXP23XX_PCI_CONTROL;
160 * master abort and cmd tgt err
162 if (temp & ((1 << 8) | (1 << 5)))
163 *IXP23XX_PCI_CONTROL = temp;
165 temp = *IXP23XX_PCI_CMDSTAT;
167 if (temp & (1 << 29))
168 *IXP23XX_PCI_CMDSTAT = temp;
169 local_irq_restore(flags);
172 * If it was an imprecise abort, then we need to correct the
173 * return address to be _after_ the instruction.
181 int clear_master_aborts(void)
185 temp = *IXP23XX_PCI_CONTROL;
188 * master abort and cmd tgt err
190 if (temp & ((1 << 8) | (1 << 5)))
191 *IXP23XX_PCI_CONTROL = temp;
193 temp = *IXP23XX_PCI_CMDSTAT;
195 if (temp & (1 << 29))
196 *IXP23XX_PCI_CMDSTAT = temp;
201 static void __init ixp23xx_pci_common_init(void)
204 *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
207 * ADDR_31 needs to be clear for PCI memory access to CPP memory
209 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
210 *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
213 * Select correct memory for PCI inbound transactions
215 if (ixp23xx_cpp_boot()) {
216 *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
218 *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
221 * Enable coherency on A2 silicon.
223 if (arch_is_coherent())
224 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
228 void __init ixp23xx_pci_preinit(void)
231 pcibios_min_mem = 0xe0000000;
235 ixp23xx_pci_common_init();
237 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
238 "PCI config cycle to non-existent device");
240 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
244 * Prevent PCI layer from seeing the inbound host-bridge resources
246 static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
251 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
252 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
253 dev->resource[i].start = 0;
254 dev->resource[i].end = 0;
255 dev->resource[i].flags = 0;
258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
261 * IXP2300 systems often have large resource requirements, so we just
262 * use our own resource space.
264 static struct resource ixp23xx_pci_mem_space = {
265 .start = IXP23XX_PCI_MEM_START,
266 .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
267 .flags = IORESOURCE_MEM,
268 .name = "PCI Mem Space"
271 static struct resource ixp23xx_pci_io_space = {
274 .flags = IORESOURCE_IO,
275 .name = "PCI I/O Space"
278 int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
283 sys->resource[0] = &ixp23xx_pci_io_space;
284 sys->resource[1] = &ixp23xx_pci_mem_space;
285 sys->resource[2] = NULL;
290 void __init ixp23xx_pci_slave_init(void)
292 ixp23xx_pci_common_init();