2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/sched.h>
21 #include <linux/tty.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_core.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/time.h>
27 #include <linux/timex.h>
28 #include <linux/clocksource.h>
29 #include <linux/clockchips.h>
33 #include <mach/hardware.h>
34 #include <asm/uaccess.h>
35 #include <asm/pgtable.h>
39 #include <asm/mach/map.h>
40 #include <asm/mach/irq.h>
41 #include <asm/mach/time.h>
43 static void __init ixp4xx_clocksource_init(void);
44 static void __init ixp4xx_clockevent_init(void);
45 static struct clock_event_device clockevent_ixp4xx;
47 /*************************************************************************
48 * IXP4xx chipset I/O mapping
49 *************************************************************************/
50 static struct map_desc ixp4xx_io_desc[] __initdata = {
51 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
52 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
53 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
54 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
56 }, { /* Expansion Bus Config Registers */
57 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
58 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
59 .length = IXP4XX_EXP_CFG_REGION_SIZE,
61 }, { /* PCI Registers */
62 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
63 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
64 .length = IXP4XX_PCI_CFG_REGION_SIZE,
67 #ifdef CONFIG_DEBUG_LL
68 { /* Debug UART mapping */
69 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
70 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
71 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
77 void __init ixp4xx_map_io(void)
79 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
83 /*************************************************************************
84 * IXP4xx chipset IRQ handling
86 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
87 * (be it PCI or something else) configures that GPIO line
89 **************************************************************************/
90 enum ixp4xx_irq_type {
91 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
94 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
95 static unsigned long long ixp4xx_irq_edge = 0;
98 * IRQ -> GPIO mapping table
100 static signed char irq2gpio[32] = {
101 -1, -1, -1, -1, -1, -1, 0, 1,
102 -1, -1, -1, -1, -1, -1, -1, -1,
103 -1, -1, -1, 2, 3, 4, 5, 6,
104 7, 8, 9, 10, 11, 12, -1, -1,
107 int gpio_to_irq(int gpio)
111 for (irq = 0; irq < 32; irq++) {
112 if (irq2gpio[irq] == gpio)
117 EXPORT_SYMBOL(gpio_to_irq);
119 int irq_to_gpio(unsigned int irq)
121 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
128 EXPORT_SYMBOL(irq_to_gpio);
130 static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
132 int line = irq2gpio[irq];
134 enum ixp4xx_irq_type irq_type;
135 volatile u32 *int_reg;
144 case IRQ_TYPE_EDGE_BOTH:
145 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
146 irq_type = IXP4XX_IRQ_EDGE;
148 case IRQ_TYPE_EDGE_RISING:
149 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
150 irq_type = IXP4XX_IRQ_EDGE;
152 case IRQ_TYPE_EDGE_FALLING:
153 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
154 irq_type = IXP4XX_IRQ_EDGE;
156 case IRQ_TYPE_LEVEL_HIGH:
157 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
158 irq_type = IXP4XX_IRQ_LEVEL;
160 case IRQ_TYPE_LEVEL_LOW:
161 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
162 irq_type = IXP4XX_IRQ_LEVEL;
168 if (irq_type == IXP4XX_IRQ_EDGE)
169 ixp4xx_irq_edge |= (1 << irq);
171 ixp4xx_irq_edge &= ~(1 << irq);
173 if (line >= 8) { /* pins 8-15 */
175 int_reg = IXP4XX_GPIO_GPIT2R;
176 } else { /* pins 0-7 */
177 int_reg = IXP4XX_GPIO_GPIT1R;
180 /* Clear the style for the appropriate pin */
181 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
182 (line * IXP4XX_GPIO_STYLE_SIZE));
184 *IXP4XX_GPIO_GPISR = (1 << line);
186 /* Set the new style */
187 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
189 /* Configure the line as an input */
190 gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN);
195 static void ixp4xx_irq_mask(unsigned int irq)
197 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
198 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
200 *IXP4XX_ICMR &= ~(1 << irq);
203 static void ixp4xx_irq_ack(unsigned int irq)
205 int line = (irq < 32) ? irq2gpio[irq] : -1;
208 *IXP4XX_GPIO_GPISR = (1 << line);
212 * Level triggered interrupts on GPIO lines can only be cleared when the
213 * interrupt condition disappears.
215 static void ixp4xx_irq_unmask(unsigned int irq)
217 if (!(ixp4xx_irq_edge & (1 << irq)))
220 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
221 *IXP4XX_ICMR2 |= (1 << (irq - 32));
223 *IXP4XX_ICMR |= (1 << irq);
226 static struct irq_chip ixp4xx_irq_chip = {
228 .ack = ixp4xx_irq_ack,
229 .mask = ixp4xx_irq_mask,
230 .unmask = ixp4xx_irq_unmask,
231 .set_type = ixp4xx_set_irq_type,
234 void __init ixp4xx_init_irq(void)
238 /* Route all sources to IRQ instead of FIQ */
241 /* Disable all interrupt */
244 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
245 /* Route upper 32 sources to IRQ instead of FIQ */
246 *IXP4XX_ICLR2 = 0x00;
248 /* Disable upper 32 interrupts */
249 *IXP4XX_ICMR2 = 0x00;
252 /* Default to all level triggered */
253 for(i = 0; i < NR_IRQS; i++) {
254 set_irq_chip(i, &ixp4xx_irq_chip);
255 set_irq_handler(i, handle_level_irq);
256 set_irq_flags(i, IRQF_VALID);
261 /*************************************************************************
263 * We use OS timer1 on the CPU for the timer tick and the timestamp
264 * counter as a source of real clock ticks to account for missed jiffies.
265 *************************************************************************/
267 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
269 struct clock_event_device *evt = dev_id;
271 /* Clear Pending Interrupt by writing '1' to it */
272 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
274 evt->event_handler(evt);
279 static struct irqaction ixp4xx_timer_irq = {
281 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
282 .handler = ixp4xx_timer_interrupt,
283 .dev_id = &clockevent_ixp4xx,
286 void __init ixp4xx_timer_init(void)
288 /* Reset/disable counter */
291 /* Clear Pending Interrupt by writing '1' to it */
292 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
294 /* Reset time-stamp counter */
297 /* Connect the interrupt handler and enable the interrupt */
298 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
300 ixp4xx_clocksource_init();
301 ixp4xx_clockevent_init();
304 struct sys_timer ixp4xx_timer = {
305 .init = ixp4xx_timer_init,
308 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
310 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
312 memcpy(&ixp4xx_udc_info, info, sizeof *info);
315 static struct resource ixp4xx_udc_resources[] = {
319 .flags = IORESOURCE_MEM,
322 .start = IRQ_IXP4XX_USB,
323 .end = IRQ_IXP4XX_USB,
324 .flags = IORESOURCE_IRQ,
329 * USB device controller. The IXP4xx uses the same controller as PXA25X,
330 * so we just use the same device.
332 static struct platform_device ixp4xx_udc_device = {
333 .name = "pxa25x-udc",
336 .resource = ixp4xx_udc_resources,
338 .platform_data = &ixp4xx_udc_info,
342 static struct platform_device *ixp4xx_devices[] __initdata = {
346 static struct resource ixp46x_i2c_resources[] = {
350 .flags = IORESOURCE_MEM,
353 .start = IRQ_IXP4XX_I2C,
354 .end = IRQ_IXP4XX_I2C,
355 .flags = IORESOURCE_IRQ
360 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
361 * we just use the same device name.
363 static struct platform_device ixp46x_i2c_controller = {
364 .name = "IOP3xx-I2C",
367 .resource = ixp46x_i2c_resources
370 static struct platform_device *ixp46x_devices[] __initdata = {
371 &ixp46x_i2c_controller
374 unsigned long ixp4xx_exp_bus_size;
375 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
377 void __init ixp4xx_sys_init(void)
379 ixp4xx_exp_bus_size = SZ_16M;
381 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
383 if (cpu_is_ixp46x()) {
386 platform_add_devices(ixp46x_devices,
387 ARRAY_SIZE(ixp46x_devices));
389 for (region = 0; region < 7; region++) {
390 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
391 ixp4xx_exp_bus_size = SZ_32M;
397 printk("IXP4xx: Using %luMiB expansion bus window size\n",
398 ixp4xx_exp_bus_size >> 20);
404 static cycle_t ixp4xx_get_cycles(struct clocksource *cs)
409 static struct clocksource clocksource_ixp4xx = {
412 .read = ixp4xx_get_cycles,
413 .mask = CLOCKSOURCE_MASK(32),
415 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
418 unsigned long ixp4xx_timer_freq = FREQ;
419 EXPORT_SYMBOL(ixp4xx_timer_freq);
420 static void __init ixp4xx_clocksource_init(void)
422 clocksource_ixp4xx.mult =
423 clocksource_hz2mult(ixp4xx_timer_freq,
424 clocksource_ixp4xx.shift);
425 clocksource_register(&clocksource_ixp4xx);
431 unsigned long long sched_clock(void)
433 cycle_t cyc = ixp4xx_get_cycles(NULL);
434 struct clocksource *cs = &clocksource_ixp4xx;
436 return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
442 static int ixp4xx_set_next_event(unsigned long evt,
443 struct clock_event_device *unused)
445 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
447 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
452 static void ixp4xx_set_mode(enum clock_event_mode mode,
453 struct clock_event_device *evt)
455 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
456 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
459 case CLOCK_EVT_MODE_PERIODIC:
460 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
461 opts = IXP4XX_OST_ENABLE;
463 case CLOCK_EVT_MODE_ONESHOT:
464 /* period set by 'set next_event' */
466 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
468 case CLOCK_EVT_MODE_SHUTDOWN:
469 opts &= ~IXP4XX_OST_ENABLE;
471 case CLOCK_EVT_MODE_RESUME:
472 opts |= IXP4XX_OST_ENABLE;
474 case CLOCK_EVT_MODE_UNUSED:
480 *IXP4XX_OSRT1 = osrt | opts;
483 static struct clock_event_device clockevent_ixp4xx = {
484 .name = "ixp4xx timer1",
485 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
488 .set_mode = ixp4xx_set_mode,
489 .set_next_event = ixp4xx_set_next_event,
492 static void __init ixp4xx_clockevent_init(void)
494 clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC,
495 clockevent_ixp4xx.shift);
496 clockevent_ixp4xx.max_delta_ns =
497 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
498 clockevent_ixp4xx.min_delta_ns =
499 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
500 clockevent_ixp4xx.cpumask = cpumask_of(0);
502 clockevents_register_device(&clockevent_ixp4xx);