2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/clocksource.h>
28 #include <linux/clockchips.h>
30 #include <linux/export.h>
31 #include <linux/gpio.h>
32 #include <linux/cpu.h>
33 #include <linux/sched_clock.h>
36 #include <mach/hardware.h>
38 #include <asm/uaccess.h>
39 #include <asm/pgtable.h>
42 #include <asm/system_misc.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/time.h>
48 static void __init ixp4xx_clocksource_init(void);
49 static void __init ixp4xx_clockevent_init(void);
50 static struct clock_event_device clockevent_ixp4xx;
52 /*************************************************************************
53 * IXP4xx chipset I/O mapping
54 *************************************************************************/
55 static struct map_desc ixp4xx_io_desc[] __initdata = {
56 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
57 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
58 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
59 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
61 }, { /* Expansion Bus Config Registers */
62 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
63 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
64 .length = IXP4XX_EXP_CFG_REGION_SIZE,
66 }, { /* PCI Registers */
67 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
68 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
69 .length = IXP4XX_PCI_CFG_REGION_SIZE,
71 }, { /* Queue Manager */
72 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
73 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
74 .length = IXP4XX_QMGR_REGION_SIZE,
79 void __init ixp4xx_map_io(void)
81 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
85 /*************************************************************************
86 * IXP4xx chipset IRQ handling
88 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
89 * (be it PCI or something else) configures that GPIO line
91 **************************************************************************/
92 enum ixp4xx_irq_type {
93 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
96 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
97 static unsigned long long ixp4xx_irq_edge = 0;
100 * IRQ -> GPIO mapping table
102 static signed char irq2gpio[32] = {
103 -1, -1, -1, -1, -1, -1, 0, 1,
104 -1, -1, -1, -1, -1, -1, -1, -1,
105 -1, -1, -1, 2, 3, 4, 5, 6,
106 7, 8, 9, 10, 11, 12, -1, -1,
109 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
113 for (irq = 0; irq < 32; irq++) {
114 if (irq2gpio[irq] == gpio)
120 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
122 int line = irq2gpio[d->irq];
124 enum ixp4xx_irq_type irq_type;
125 volatile u32 *int_reg;
134 case IRQ_TYPE_EDGE_BOTH:
135 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
136 irq_type = IXP4XX_IRQ_EDGE;
138 case IRQ_TYPE_EDGE_RISING:
139 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
140 irq_type = IXP4XX_IRQ_EDGE;
142 case IRQ_TYPE_EDGE_FALLING:
143 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
144 irq_type = IXP4XX_IRQ_EDGE;
146 case IRQ_TYPE_LEVEL_HIGH:
147 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
148 irq_type = IXP4XX_IRQ_LEVEL;
150 case IRQ_TYPE_LEVEL_LOW:
151 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
152 irq_type = IXP4XX_IRQ_LEVEL;
158 if (irq_type == IXP4XX_IRQ_EDGE)
159 ixp4xx_irq_edge |= (1 << d->irq);
161 ixp4xx_irq_edge &= ~(1 << d->irq);
163 if (line >= 8) { /* pins 8-15 */
165 int_reg = IXP4XX_GPIO_GPIT2R;
166 } else { /* pins 0-7 */
167 int_reg = IXP4XX_GPIO_GPIT1R;
170 /* Clear the style for the appropriate pin */
171 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
172 (line * IXP4XX_GPIO_STYLE_SIZE));
174 *IXP4XX_GPIO_GPISR = (1 << line);
176 /* Set the new style */
177 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
179 /* Configure the line as an input */
180 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
185 static void ixp4xx_irq_mask(struct irq_data *d)
187 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
188 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
190 *IXP4XX_ICMR &= ~(1 << d->irq);
193 static void ixp4xx_irq_ack(struct irq_data *d)
195 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
198 *IXP4XX_GPIO_GPISR = (1 << line);
202 * Level triggered interrupts on GPIO lines can only be cleared when the
203 * interrupt condition disappears.
205 static void ixp4xx_irq_unmask(struct irq_data *d)
207 if (!(ixp4xx_irq_edge & (1 << d->irq)))
210 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
211 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
213 *IXP4XX_ICMR |= (1 << d->irq);
216 static struct irq_chip ixp4xx_irq_chip = {
218 .irq_ack = ixp4xx_irq_ack,
219 .irq_mask = ixp4xx_irq_mask,
220 .irq_unmask = ixp4xx_irq_unmask,
221 .irq_set_type = ixp4xx_set_irq_type,
224 void __init ixp4xx_init_irq(void)
229 * ixp4xx does not implement the XScale PWRMODE register
230 * so it must not call cpu_do_idle().
232 cpu_idle_poll_ctrl(true);
234 /* Route all sources to IRQ instead of FIQ */
237 /* Disable all interrupt */
240 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
241 /* Route upper 32 sources to IRQ instead of FIQ */
242 *IXP4XX_ICLR2 = 0x00;
244 /* Disable upper 32 interrupts */
245 *IXP4XX_ICMR2 = 0x00;
248 /* Default to all level triggered */
249 for(i = 0; i < NR_IRQS; i++) {
250 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
252 set_irq_flags(i, IRQF_VALID);
257 /*************************************************************************
259 * We use OS timer1 on the CPU for the timer tick and the timestamp
260 * counter as a source of real clock ticks to account for missed jiffies.
261 *************************************************************************/
263 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
265 struct clock_event_device *evt = dev_id;
267 /* Clear Pending Interrupt by writing '1' to it */
268 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
270 evt->event_handler(evt);
275 static struct irqaction ixp4xx_timer_irq = {
277 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
278 .handler = ixp4xx_timer_interrupt,
279 .dev_id = &clockevent_ixp4xx,
282 void __init ixp4xx_timer_init(void)
284 /* Reset/disable counter */
287 /* Clear Pending Interrupt by writing '1' to it */
288 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
290 /* Reset time-stamp counter */
293 /* Connect the interrupt handler and enable the interrupt */
294 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
296 ixp4xx_clocksource_init();
297 ixp4xx_clockevent_init();
300 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
302 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
304 memcpy(&ixp4xx_udc_info, info, sizeof *info);
307 static struct resource ixp4xx_udc_resources[] = {
311 .flags = IORESOURCE_MEM,
314 .start = IRQ_IXP4XX_USB,
315 .end = IRQ_IXP4XX_USB,
316 .flags = IORESOURCE_IRQ,
321 * USB device controller. The IXP4xx uses the same controller as PXA25X,
322 * so we just use the same device.
324 static struct platform_device ixp4xx_udc_device = {
325 .name = "pxa25x-udc",
328 .resource = ixp4xx_udc_resources,
330 .platform_data = &ixp4xx_udc_info,
334 static struct platform_device *ixp4xx_devices[] __initdata = {
338 static struct resource ixp46x_i2c_resources[] = {
342 .flags = IORESOURCE_MEM,
345 .start = IRQ_IXP4XX_I2C,
346 .end = IRQ_IXP4XX_I2C,
347 .flags = IORESOURCE_IRQ
352 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
353 * we just use the same device name.
355 static struct platform_device ixp46x_i2c_controller = {
356 .name = "IOP3xx-I2C",
359 .resource = ixp46x_i2c_resources
362 static struct platform_device *ixp46x_devices[] __initdata = {
363 &ixp46x_i2c_controller
366 unsigned long ixp4xx_exp_bus_size;
367 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
369 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
371 gpio_line_config(gpio, IXP4XX_GPIO_IN);
376 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
379 gpio_line_set(gpio, level);
380 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
385 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
389 gpio_line_get(gpio, &value);
394 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
397 gpio_line_set(gpio, value);
400 static struct gpio_chip ixp4xx_gpio_chip = {
401 .label = "IXP4XX_GPIO_CHIP",
402 .direction_input = ixp4xx_gpio_direction_input,
403 .direction_output = ixp4xx_gpio_direction_output,
404 .get = ixp4xx_gpio_get_value,
405 .set = ixp4xx_gpio_set_value,
406 .to_irq = ixp4xx_gpio_to_irq,
411 void __init ixp4xx_sys_init(void)
413 ixp4xx_exp_bus_size = SZ_16M;
415 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
417 gpiochip_add(&ixp4xx_gpio_chip);
419 if (cpu_is_ixp46x()) {
422 platform_add_devices(ixp46x_devices,
423 ARRAY_SIZE(ixp46x_devices));
425 for (region = 0; region < 7; region++) {
426 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
427 ixp4xx_exp_bus_size = SZ_32M;
433 printk("IXP4xx: Using %luMiB expansion bus window size\n",
434 ixp4xx_exp_bus_size >> 20);
440 static u32 notrace ixp4xx_read_sched_clock(void)
449 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
454 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
455 EXPORT_SYMBOL(ixp4xx_timer_freq);
456 static void __init ixp4xx_clocksource_init(void)
458 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
460 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
461 ixp4xx_clocksource_read);
467 static int ixp4xx_set_next_event(unsigned long evt,
468 struct clock_event_device *unused)
470 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
472 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
477 static void ixp4xx_set_mode(enum clock_event_mode mode,
478 struct clock_event_device *evt)
480 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
481 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
484 case CLOCK_EVT_MODE_PERIODIC:
485 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
486 opts = IXP4XX_OST_ENABLE;
488 case CLOCK_EVT_MODE_ONESHOT:
489 /* period set by 'set next_event' */
491 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
493 case CLOCK_EVT_MODE_SHUTDOWN:
494 opts &= ~IXP4XX_OST_ENABLE;
496 case CLOCK_EVT_MODE_RESUME:
497 opts |= IXP4XX_OST_ENABLE;
499 case CLOCK_EVT_MODE_UNUSED:
505 *IXP4XX_OSRT1 = osrt | opts;
508 static struct clock_event_device clockevent_ixp4xx = {
509 .name = "ixp4xx timer1",
510 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
512 .set_mode = ixp4xx_set_mode,
513 .set_next_event = ixp4xx_set_next_event,
516 static void __init ixp4xx_clockevent_init(void)
518 clockevent_ixp4xx.cpumask = cpumask_of(0);
519 clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
523 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
525 if ( 1 && mode == REBOOT_SOFT) {
526 /* Jump into ROM at address 0 */
529 /* Use on-chip reset capability */
531 /* set the "key" register to enable access to
532 * "timer" and "enable" registers
534 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
536 /* write 0 to the timer register for an immediate reset */
539 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
543 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
545 * In the case of using indirect PCI, we simply return the actual PCI
546 * address and our read/write implementation use that to drive the
547 * access registers. If something outside of PCI is ioremap'd, we
548 * fallback to the default.
551 static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
552 unsigned int mtype, void *caller)
554 if (!is_pci_memory(addr))
555 return __arm_ioremap_caller(addr, size, mtype, caller);
557 return (void __iomem *)addr;
560 static void ixp4xx_iounmap(void __iomem *addr)
562 if (!is_pci_memory((__force u32)addr))
566 void __init ixp4xx_init_early(void)
568 arch_ioremap_caller = ixp4xx_ioremap_caller;
569 arch_iounmap = ixp4xx_iounmap;
572 void __init ixp4xx_init_early(void) {}