2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/clocksource.h>
28 #include <linux/clockchips.h>
30 #include <linux/export.h>
33 #include <mach/hardware.h>
34 #include <asm/uaccess.h>
35 #include <asm/pgtable.h>
38 #include <asm/sched_clock.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
44 static void __init ixp4xx_clocksource_init(void);
45 static void __init ixp4xx_clockevent_init(void);
46 static struct clock_event_device clockevent_ixp4xx;
48 /*************************************************************************
49 * IXP4xx chipset I/O mapping
50 *************************************************************************/
51 static struct map_desc ixp4xx_io_desc[] __initdata = {
52 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
53 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
54 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
55 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
57 }, { /* Expansion Bus Config Registers */
58 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
59 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
60 .length = IXP4XX_EXP_CFG_REGION_SIZE,
62 }, { /* PCI Registers */
63 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
64 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
65 .length = IXP4XX_PCI_CFG_REGION_SIZE,
68 #ifdef CONFIG_DEBUG_LL
69 { /* Debug UART mapping */
70 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
71 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
72 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
78 void __init ixp4xx_map_io(void)
80 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
84 /*************************************************************************
85 * IXP4xx chipset IRQ handling
87 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
88 * (be it PCI or something else) configures that GPIO line
90 **************************************************************************/
91 enum ixp4xx_irq_type {
92 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
95 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
96 static unsigned long long ixp4xx_irq_edge = 0;
99 * IRQ -> GPIO mapping table
101 static signed char irq2gpio[32] = {
102 -1, -1, -1, -1, -1, -1, 0, 1,
103 -1, -1, -1, -1, -1, -1, -1, -1,
104 -1, -1, -1, 2, 3, 4, 5, 6,
105 7, 8, 9, 10, 11, 12, -1, -1,
108 int gpio_to_irq(int gpio)
112 for (irq = 0; irq < 32; irq++) {
113 if (irq2gpio[irq] == gpio)
118 EXPORT_SYMBOL(gpio_to_irq);
120 int irq_to_gpio(unsigned int irq)
122 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
129 EXPORT_SYMBOL(irq_to_gpio);
131 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
133 int line = irq2gpio[d->irq];
135 enum ixp4xx_irq_type irq_type;
136 volatile u32 *int_reg;
145 case IRQ_TYPE_EDGE_BOTH:
146 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
147 irq_type = IXP4XX_IRQ_EDGE;
149 case IRQ_TYPE_EDGE_RISING:
150 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
151 irq_type = IXP4XX_IRQ_EDGE;
153 case IRQ_TYPE_EDGE_FALLING:
154 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
155 irq_type = IXP4XX_IRQ_EDGE;
157 case IRQ_TYPE_LEVEL_HIGH:
158 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
159 irq_type = IXP4XX_IRQ_LEVEL;
161 case IRQ_TYPE_LEVEL_LOW:
162 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
163 irq_type = IXP4XX_IRQ_LEVEL;
169 if (irq_type == IXP4XX_IRQ_EDGE)
170 ixp4xx_irq_edge |= (1 << d->irq);
172 ixp4xx_irq_edge &= ~(1 << d->irq);
174 if (line >= 8) { /* pins 8-15 */
176 int_reg = IXP4XX_GPIO_GPIT2R;
177 } else { /* pins 0-7 */
178 int_reg = IXP4XX_GPIO_GPIT1R;
181 /* Clear the style for the appropriate pin */
182 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
183 (line * IXP4XX_GPIO_STYLE_SIZE));
185 *IXP4XX_GPIO_GPISR = (1 << line);
187 /* Set the new style */
188 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
190 /* Configure the line as an input */
191 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
196 static void ixp4xx_irq_mask(struct irq_data *d)
198 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
199 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
201 *IXP4XX_ICMR &= ~(1 << d->irq);
204 static void ixp4xx_irq_ack(struct irq_data *d)
206 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
209 *IXP4XX_GPIO_GPISR = (1 << line);
213 * Level triggered interrupts on GPIO lines can only be cleared when the
214 * interrupt condition disappears.
216 static void ixp4xx_irq_unmask(struct irq_data *d)
218 if (!(ixp4xx_irq_edge & (1 << d->irq)))
221 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
222 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
224 *IXP4XX_ICMR |= (1 << d->irq);
227 static struct irq_chip ixp4xx_irq_chip = {
229 .irq_ack = ixp4xx_irq_ack,
230 .irq_mask = ixp4xx_irq_mask,
231 .irq_unmask = ixp4xx_irq_unmask,
232 .irq_set_type = ixp4xx_set_irq_type,
235 void __init ixp4xx_init_irq(void)
240 * ixp4xx does not implement the XScale PWRMODE register
241 * so it must not call cpu_do_idle().
245 /* Route all sources to IRQ instead of FIQ */
248 /* Disable all interrupt */
251 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
252 /* Route upper 32 sources to IRQ instead of FIQ */
253 *IXP4XX_ICLR2 = 0x00;
255 /* Disable upper 32 interrupts */
256 *IXP4XX_ICMR2 = 0x00;
259 /* Default to all level triggered */
260 for(i = 0; i < NR_IRQS; i++) {
261 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
263 set_irq_flags(i, IRQF_VALID);
268 /*************************************************************************
270 * We use OS timer1 on the CPU for the timer tick and the timestamp
271 * counter as a source of real clock ticks to account for missed jiffies.
272 *************************************************************************/
274 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
276 struct clock_event_device *evt = dev_id;
278 /* Clear Pending Interrupt by writing '1' to it */
279 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
281 evt->event_handler(evt);
286 static struct irqaction ixp4xx_timer_irq = {
288 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
289 .handler = ixp4xx_timer_interrupt,
290 .dev_id = &clockevent_ixp4xx,
293 void __init ixp4xx_timer_init(void)
295 /* Reset/disable counter */
298 /* Clear Pending Interrupt by writing '1' to it */
299 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
301 /* Reset time-stamp counter */
304 /* Connect the interrupt handler and enable the interrupt */
305 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
307 ixp4xx_clocksource_init();
308 ixp4xx_clockevent_init();
311 struct sys_timer ixp4xx_timer = {
312 .init = ixp4xx_timer_init,
315 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
317 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
319 memcpy(&ixp4xx_udc_info, info, sizeof *info);
322 static struct resource ixp4xx_udc_resources[] = {
326 .flags = IORESOURCE_MEM,
329 .start = IRQ_IXP4XX_USB,
330 .end = IRQ_IXP4XX_USB,
331 .flags = IORESOURCE_IRQ,
336 * USB device controller. The IXP4xx uses the same controller as PXA25X,
337 * so we just use the same device.
339 static struct platform_device ixp4xx_udc_device = {
340 .name = "pxa25x-udc",
343 .resource = ixp4xx_udc_resources,
345 .platform_data = &ixp4xx_udc_info,
349 static struct platform_device *ixp4xx_devices[] __initdata = {
353 static struct resource ixp46x_i2c_resources[] = {
357 .flags = IORESOURCE_MEM,
360 .start = IRQ_IXP4XX_I2C,
361 .end = IRQ_IXP4XX_I2C,
362 .flags = IORESOURCE_IRQ
367 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
368 * we just use the same device name.
370 static struct platform_device ixp46x_i2c_controller = {
371 .name = "IOP3xx-I2C",
374 .resource = ixp46x_i2c_resources
377 static struct platform_device *ixp46x_devices[] __initdata = {
378 &ixp46x_i2c_controller
381 unsigned long ixp4xx_exp_bus_size;
382 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
384 void __init ixp4xx_sys_init(void)
386 ixp4xx_exp_bus_size = SZ_16M;
388 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
390 if (cpu_is_ixp46x()) {
393 platform_add_devices(ixp46x_devices,
394 ARRAY_SIZE(ixp46x_devices));
396 for (region = 0; region < 7; region++) {
397 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
398 ixp4xx_exp_bus_size = SZ_32M;
404 printk("IXP4xx: Using %luMiB expansion bus window size\n",
405 ixp4xx_exp_bus_size >> 20);
411 static u32 notrace ixp4xx_read_sched_clock(void)
420 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
425 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
426 EXPORT_SYMBOL(ixp4xx_timer_freq);
427 static void __init ixp4xx_clocksource_init(void)
429 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
431 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
432 ixp4xx_clocksource_read);
438 static int ixp4xx_set_next_event(unsigned long evt,
439 struct clock_event_device *unused)
441 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
443 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
448 static void ixp4xx_set_mode(enum clock_event_mode mode,
449 struct clock_event_device *evt)
451 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
452 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
455 case CLOCK_EVT_MODE_PERIODIC:
456 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
457 opts = IXP4XX_OST_ENABLE;
459 case CLOCK_EVT_MODE_ONESHOT:
460 /* period set by 'set next_event' */
462 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
464 case CLOCK_EVT_MODE_SHUTDOWN:
465 opts &= ~IXP4XX_OST_ENABLE;
467 case CLOCK_EVT_MODE_RESUME:
468 opts |= IXP4XX_OST_ENABLE;
470 case CLOCK_EVT_MODE_UNUSED:
476 *IXP4XX_OSRT1 = osrt | opts;
479 static struct clock_event_device clockevent_ixp4xx = {
480 .name = "ixp4xx timer1",
481 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
484 .set_mode = ixp4xx_set_mode,
485 .set_next_event = ixp4xx_set_next_event,
488 static void __init ixp4xx_clockevent_init(void)
490 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
491 clockevent_ixp4xx.shift);
492 clockevent_ixp4xx.max_delta_ns =
493 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
494 clockevent_ixp4xx.min_delta_ns =
495 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
496 clockevent_ixp4xx.cpumask = cpumask_of(0);
498 clockevents_register_device(&clockevent_ixp4xx);
501 void ixp4xx_restart(char mode, const char *cmd)
503 if ( 1 && mode == 's') {
504 /* Jump into ROM at address 0 */
507 /* Use on-chip reset capability */
509 /* set the "key" register to enable access to
510 * "timer" and "enable" registers
512 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
514 /* write 0 to the timer register for an immediate reset */
517 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;